The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/arm/hisilicon/hisilicon.txt

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    1 Hisilicon Platforms Device Tree Bindings
    2 ----------------------------------------------------
    3 Hi3660 SoC
    4 Required root node properties:
    5         - compatible = "hisilicon,hi3660";
    6 
    7 HiKey960 Board
    8 Required root node properties:
    9         - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
   10 
   11 Hi3670 SoC
   12 Required root node properties:
   13         - compatible = "hisilicon,hi3670";
   14 
   15 HiKey970 Board
   16 Required root node properties:
   17         - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
   18 
   19 Hi3798cv200 SoC
   20 Required root node properties:
   21         - compatible = "hisilicon,hi3798cv200";
   22 
   23 Hi3798cv200 Poplar Board
   24 Required root node properties:
   25         - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
   26 
   27 Hi4511 Board
   28 Required root node properties:
   29         - compatible = "hisilicon,hi3620-hi4511";
   30 
   31 Hi6220 SoC
   32 Required root node properties:
   33         - compatible = "hisilicon,hi6220";
   34 
   35 HiKey Board
   36 Required root node properties:
   37         - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
   38 
   39 HiP01 ca9x2 Board
   40 Required root node properties:
   41         - compatible = "hisilicon,hip01-ca9x2";
   42 
   43 HiP04 D01 Board
   44 Required root node properties:
   45         - compatible = "hisilicon,hip04-d01";
   46 
   47 HiP05 D02 Board
   48 Required root node properties:
   49         - compatible = "hisilicon,hip05-d02";
   50 
   51 HiP06 D03 Board
   52 Required root node properties:
   53         - compatible = "hisilicon,hip06-d03";
   54 
   55 HiP07 D05 Board
   56 Required root node properties:
   57         - compatible = "hisilicon,hip07-d05";
   58 
   59 Hisilicon system controller
   60 
   61 Required properties:
   62 - compatible : "hisilicon,sysctrl"
   63 - reg : Register address and size
   64 
   65 Optional properties:
   66 - smp-offset : offset in sysctrl for notifying slave cpu booting
   67                 cpu 1, reg;
   68                 cpu 2, reg + 0x4;
   69                 cpu 3, reg + 0x8;
   70                 If reg value is not zero, cpun exit wfi and go
   71 - resume-offset : offset in sysctrl for notifying cpu0 when resume
   72 - reboot-offset : offset in sysctrl for system reboot
   73 
   74 Example:
   75 
   76         /* for Hi3620 */
   77         sysctrl: system-controller@fc802000 {
   78                 compatible = "hisilicon,sysctrl";
   79                 reg = <0xfc802000 0x1000>;
   80                 smp-offset = <0x31c>;
   81                 resume-offset = <0x308>;
   82                 reboot-offset = <0x4>;
   83         };
   84 
   85 -----------------------------------------------------------------------
   86 Hisilicon Hi3798CV200 Peripheral Controller
   87 
   88 The Hi3798CV200 Peripheral Controller controls peripherals, queries
   89 their status, and configures some functions of peripherals.
   90 
   91 Required properties:
   92 - compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
   93   and "simple-mfd".
   94 - reg: Register address and size of Peripheral Controller.
   95 - #address-cells: Should be 1.
   96 - #size-cells: Should be 1.
   97 
   98 Examples:
   99 
  100         perictrl: peripheral-controller@8a20000 {
  101                 compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
  102                              "simple-mfd";
  103                 reg = <0x8a20000 0x1000>;
  104                 #address-cells = <1>;
  105                 #size-cells = <1>;
  106         };
  107 
  108 -----------------------------------------------------------------------
  109 Hisilicon Hi6220 system controller
  110 
  111 Required properties:
  112 - compatible : "hisilicon,hi6220-sysctrl"
  113 - reg : Register address and size
  114 - #clock-cells: should be set to 1, many clock registers are defined
  115   under this controller and this property must be present.
  116 
  117 Hisilicon designs this controller as one of the system controllers,
  118 its main functions are the same as Hisilicon system controller, but
  119 the register offset of some core modules are different.
  120 
  121 Example:
  122         /*for Hi6220*/
  123         sys_ctrl: sys_ctrl@f7030000 {
  124                 compatible = "hisilicon,hi6220-sysctrl", "syscon";
  125                 reg = <0x0 0xf7030000 0x0 0x2000>;
  126                 #clock-cells = <1>;
  127         };
  128 
  129 
  130 Hisilicon Hi6220 Power Always ON domain controller
  131 
  132 Required properties:
  133 - compatible : "hisilicon,hi6220-aoctrl"
  134 - reg : Register address and size
  135 - #clock-cells: should be set to 1, many clock registers are defined
  136   under this controller and this property must be present.
  137 
  138 Hisilicon designs this system controller to control the power always
  139 on domain for mobile platform.
  140 
  141 Example:
  142         /*for Hi6220*/
  143         ao_ctrl: ao_ctrl@f7800000 {
  144                 compatible = "hisilicon,hi6220-aoctrl", "syscon";
  145                 reg = <0x0 0xf7800000 0x0 0x2000>;
  146                 #clock-cells = <1>;
  147         };
  148 
  149 
  150 Hisilicon Hi6220 Media domain controller
  151 
  152 Required properties:
  153 - compatible : "hisilicon,hi6220-mediactrl"
  154 - reg : Register address and size
  155 - #clock-cells: should be set to 1, many clock registers are defined
  156   under this controller and this property must be present.
  157 
  158 Hisilicon designs this system controller to control the multimedia
  159 domain(e.g. codec, G3D ...) for mobile platform.
  160 
  161 Example:
  162         /*for Hi6220*/
  163         media_ctrl: media_ctrl@f4410000 {
  164                 compatible = "hisilicon,hi6220-mediactrl", "syscon";
  165                 reg = <0x0 0xf4410000 0x0 0x1000>;
  166                 #clock-cells = <1>;
  167         };
  168 
  169 
  170 Hisilicon Hi6220 Power Management domain controller
  171 
  172 Required properties:
  173 - compatible : "hisilicon,hi6220-pmctrl"
  174 - reg : Register address and size
  175 - #clock-cells: should be set to 1, some clock registers are define
  176   under this controller and this property must be present.
  177 
  178 Hisilicon designs this system controller to control the power management
  179 domain for mobile platform.
  180 
  181 Example:
  182         /*for Hi6220*/
  183         pm_ctrl: pm_ctrl@f7032000 {
  184                 compatible = "hisilicon,hi6220-pmctrl", "syscon";
  185                 reg = <0x0 0xf7032000 0x0 0x1000>;
  186                 #clock-cells = <1>;
  187         };
  188 
  189 
  190 Hisilicon Hi6220 SRAM controller
  191 
  192 Required properties:
  193 - compatible : "hisilicon,hi6220-sramctrl", "syscon"
  194 - reg : Register address and size
  195 
  196 Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
  197 SRAM banks for power management, modem, security, etc. Further, use "syscon"
  198 managing the common sram which can be shared by multiple modules.
  199 
  200 Example:
  201         /*for Hi6220*/
  202         sram: sram@fff80000 {
  203                 compatible = "hisilicon,hi6220-sramctrl", "syscon";
  204                 reg = <0x0 0xfff80000 0x0 0x12000>;
  205         };
  206 
  207 -----------------------------------------------------------------------
  208 Hisilicon HiP01 system controller
  209 
  210 Required properties:
  211 - compatible : "hisilicon,hip01-sysctrl"
  212 - reg : Register address and size
  213 
  214 The HiP01 system controller is mostly compatible with hisilicon
  215 system controller,but it has some specific control registers for
  216 HIP01 SoC family, such as slave core boot, and also some same
  217 registers located at different offset.
  218 
  219 Example:
  220 
  221         /* for hip01-ca9x2 */
  222         sysctrl: system-controller@10000000 {
  223                 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
  224                 reg = <0x10000000 0x1000>;
  225                 reboot-offset = <0x4>;
  226         };
  227 
  228 -----------------------------------------------------------------------
  229 Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
  230 
  231 Required properties:
  232 - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
  233 - reg : Register address and size
  234 
  235 The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
  236 HiP05 or HiP06 Soc to implement some basic configurations.
  237 
  238 Example:
  239         /* for HiP05 PCIe-SAS sub system */
  240         pcie_sas: system_controller@b0000000 {
  241                 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
  242                 reg = <0xb0000000 0x10000>;
  243         };
  244 
  245 Hisilicon HiP05/HiP06 PERI sub system controller
  246 
  247 Required properties:
  248 - compatible : "hisilicon,peri-subctrl", "syscon";
  249 - reg : Register address and size
  250 
  251 The PERI sub system controller is shared by peripheral controllers in
  252 HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
  253 controllers include mdio, ddr, iic, uart, timer and so on.
  254 
  255 Example:
  256         /* for HiP05 sub peri system */
  257         peri_c_subctrl: syscon@80000000 {
  258                 compatible = "hisilicon,peri-subctrl", "syscon";
  259                 reg = <0x0 0x80000000 0x0 0x10000>;
  260         };
  261 
  262 Hisilicon HiP05/HiP06 DSA sub system controller
  263 
  264 Required properties:
  265 - compatible : "hisilicon,dsa-subctrl", "syscon";
  266 - reg : Register address and size
  267 
  268 The DSA sub system controller is shared by peripheral controllers in
  269 HiP05 or HiP06 Soc to implement some basic configurations.
  270 
  271 Example:
  272         /* for HiP05 dsa sub system */
  273         pcie_sas: system_controller@a0000000 {
  274                 compatible = "hisilicon,dsa-subctrl", "syscon";
  275                 reg = <0xa0000000 0x10000>;
  276         };
  277 
  278 -----------------------------------------------------------------------
  279 Hisilicon CPU controller
  280 
  281 Required properties:
  282 - compatible : "hisilicon,cpuctrl"
  283 - reg : Register address and size
  284 
  285 The clock registers and power registers of secondary cores are defined
  286 in CPU controller, especially in HIX5HD2 SoC.
  287 
  288 -----------------------------------------------------------------------
  289 PCTRL: Peripheral misc control register
  290 
  291 Required Properties:
  292 - compatible: "hisilicon,pctrl"
  293 - reg: Address and size of pctrl.
  294 
  295 Example:
  296 
  297         /* for Hi3620 */
  298         pctrl: pctrl@fca09000 {
  299                 compatible = "hisilicon,pctrl";
  300                 reg = <0xfca09000 0x1000>;
  301         };
  302 
  303 -----------------------------------------------------------------------
  304 Fabric:
  305 
  306 Required Properties:
  307 - compatible: "hisilicon,hip04-fabric";
  308 - reg: Address and size of Fabric
  309 
  310 -----------------------------------------------------------------------
  311 Bootwrapper boot method (software protocol on SMP):
  312 
  313 Required Properties:
  314 - compatible: "hisilicon,hip04-bootwrapper";
  315 - boot-method: Address and size of boot method.
  316   [0]: bootwrapper physical address
  317   [1]: bootwrapper size
  318   [2]: relocation physical address
  319   [3]: relocation size

Cache object: 577035376bfaf09fb8300d56e692e400


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