pmu.yaml

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10

    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: ARM Performance Monitor Units
    8 
    9 maintainers:
   10   - Mark Rutland <mark.rutland@arm.com>
   11   - Will Deacon <will.deacon@arm.com>
   12 
   13 description: |+
   14   ARM cores often have a PMU for counting cpu and cache events like cache misses
   15   and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
   16   representation in the device tree should be done as under:-
   17 
   18 properties:
   19   compatible:
   20     items:
   21       - enum:
   22           - apm,potenza-pmu
   23           - apple,firestorm-pmu
   24           - apple,icestorm-pmu
   25           - arm,armv8-pmuv3 # Only for s/w models
   26           - arm,arm1136-pmu
   27           - arm,arm1176-pmu
   28           - arm,arm11mpcore-pmu
   29           - arm,cortex-a5-pmu
   30           - arm,cortex-a7-pmu
   31           - arm,cortex-a8-pmu
   32           - arm,cortex-a9-pmu
   33           - arm,cortex-a12-pmu
   34           - arm,cortex-a15-pmu
   35           - arm,cortex-a17-pmu
   36           - arm,cortex-a32-pmu
   37           - arm,cortex-a34-pmu
   38           - arm,cortex-a35-pmu
   39           - arm,cortex-a53-pmu
   40           - arm,cortex-a55-pmu
   41           - arm,cortex-a57-pmu
   42           - arm,cortex-a65-pmu
   43           - arm,cortex-a72-pmu
   44           - arm,cortex-a73-pmu
   45           - arm,cortex-a75-pmu
   46           - arm,cortex-a76-pmu
   47           - arm,cortex-a77-pmu
   48           - arm,cortex-a78-pmu
   49           - arm,cortex-a510-pmu
   50           - arm,cortex-a710-pmu
   51           - arm,cortex-x1-pmu
   52           - arm,cortex-x2-pmu
   53           - arm,neoverse-e1-pmu
   54           - arm,neoverse-n1-pmu
   55           - arm,neoverse-n2-pmu
   56           - arm,neoverse-v1-pmu
   57           - brcm,vulcan-pmu
   58           - cavium,thunder-pmu
   59           - nvidia,denver-pmu
   60           - nvidia,carmel-pmu
   61           - qcom,krait-pmu
   62           - qcom,scorpion-pmu
   63           - qcom,scorpion-mp-pmu
   64 
   65   interrupts:
   66     # Don't know how many CPUs, so no constraints to specify
   67     description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
   68 
   69   interrupt-affinity:
   70     $ref: /schemas/types.yaml#/definitions/phandle-array
   71     items:
   72       maxItems: 1
   73     description:
   74       When using SPIs, specifies a list of phandles to CPU
   75       nodes corresponding directly to the affinity of
   76       the SPIs listed in the interrupts property.
   77 
   78       When using a PPI, specifies a list of phandles to CPU
   79       nodes corresponding to the set of CPUs which have
   80       a PMU of this type signalling the PPI listed in the
   81       interrupts property, unless this is already specified
   82       by the PPI interrupt specifier itself (in which case
   83       the interrupt-affinity property shouldn't be present).
   84 
   85       This property should be present when there is more than
   86       a single SPI.
   87 
   88   qcom,no-pc-write:
   89     type: boolean
   90     description:
   91       Indicates that this PMU doesn't support the 0xc and 0xd events.
   92 
   93   secure-reg-access:
   94     type: boolean
   95     description:
   96       Indicates that the ARMv7 Secure Debug Enable Register
   97       (SDER) is accessible. This will cause the driver to do
   98       any setup required that is only possible in ARMv7 secure
   99       state. If not present the ARMv7 SDER will not be touched,
  100       which means the PMU may fail to operate unless external
  101       code (bootloader or security monitor) has performed the
  102       appropriate initialisation. Note that this property is
  103       not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
  104       in Non-secure state.
  105 
  106 required:
  107   - compatible
  108 
  109 additionalProperties: false
  110 
  111 ...

Cache object: 3860e6fc947fdc5106b5386d99e9ac36

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.

FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/arm/pmu.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/arm/pmu.yaml