socionext,uniphier-system-cache.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: UniPhier outer cache controller
    8 
    9 description: |
   10   UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
   11   controller system. All of them have a level 2 cache controller, and some
   12   have a level 3 cache controller as well.
   13 
   14 maintainers:
   15   - Masahiro Yamada <yamada.masahiro@socionext.com>
   16 
   17 properties:
   18   compatible:
   19     const: socionext,uniphier-system-cache
   20 
   21   reg:
   22     description: |
   23       should contain 3 regions: control register, revision register,
   24       operation register, in this order.
   25     minItems: 3
   26     maxItems: 3
   27 
   28   interrupts:
   29     description: |
   30       Interrupts can be used to notify the completion of cache operations.
   31       The number of interrupts should match to the number of CPU cores.
   32       The specified interrupts correspond to CPU0, CPU1, ... in this order.
   33     minItems: 1
   34     maxItems: 4
   35 
   36   cache-unified: true
   37 
   38   cache-size: true
   39 
   40   cache-sets: true
   41 
   42   cache-line-size: true
   43 
   44   cache-level:
   45     minimum: 2
   46     maximum: 3
   47 
   48   next-level-cache: true
   49 
   50 allOf:
   51   - $ref: /schemas/cache-controller.yaml#
   52 
   53 additionalProperties: false
   54 
   55 required:
   56   - compatible
   57   - reg
   58   - interrupts
   59   - cache-unified
   60   - cache-size
   61   - cache-sets
   62   - cache-line-size
   63   - cache-level
   64 
   65 examples:
   66   - |
   67     // System with L2.
   68     cache-controller@500c0000 {
   69         compatible = "socionext,uniphier-system-cache";
   70         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
   71         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
   72         cache-unified;
   73         cache-size = <0x140000>;
   74         cache-sets = <512>;
   75         cache-line-size = <128>;
   76         cache-level = <2>;
   77     };
   78   - |
   79     // System with L2 and L3.
   80     //   L2 should specify the next level cache by 'next-level-cache'.
   81     l2: cache-controller@500c0000 {
   82         compatible = "socionext,uniphier-system-cache";
   83         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
   84         interrupts = <0 190 4>, <0 191 4>;
   85         cache-unified;
   86         cache-size = <0x200000>;
   87         cache-sets = <512>;
   88         cache-line-size = <128>;
   89         cache-level = <2>;
   90         next-level-cache = <&l3>;
   91     };
   92 
   93     l3: cache-controller@500c8000 {
   94         compatible = "socionext,uniphier-system-cache";
   95         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
   96         interrupts = <0 174 4>, <0 175 4>;
   97         cache-unified;
   98         cache-size = <0x200000>;
   99         cache-sets = <512>;
  100         cache-line-size = <256>;
  101         cache-level = <3>;
  102     };

Cache object: 853748283e688d93f382f7693ac475b3

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml