nvidia,tegra186-pmc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: NVIDIA Tegra Power Management Controller (PMC)
    8 
    9 maintainers:
   10   - Thierry Reding <thierry.reding@gmail.com>
   11   - Jon Hunter <jonathanh@nvidia.com>
   12 
   13 properties:
   14   compatible:
   15     enum:
   16       - nvidia,tegra186-pmc
   17       - nvidia,tegra194-pmc
   18       - nvidia,tegra234-pmc
   19 
   20   reg:
   21     minItems: 4
   22     maxItems: 5
   23 
   24   reg-names:
   25     minItems: 4
   26     items:
   27       - const: pmc
   28       - const: wake
   29       - const: aotag
   30       - const: scratch
   31       - const: misc
   32 
   33   interrupt-controller: true
   34 
   35   "#interrupt-cells":
   36     description: Specifies the number of cells needed to encode an
   37       interrupt source. The value must be 2.
   38     const: 2
   39 
   40   nvidia,invert-interrupt:
   41     description: If present, inverts the PMU interrupt signal.
   42     $ref: /schemas/types.yaml#/definitions/flag
   43 
   44 if:
   45   properties:
   46     compatible:
   47       contains:
   48         const: nvidia,tegra186-pmc
   49 then:
   50   properties:
   51     reg:
   52       maxItems: 4
   53 
   54     reg-names:
   55       maxItems: 4
   56 else:
   57   properties:
   58     reg:
   59       minItems: 5
   60 
   61     reg-names:
   62       minItems: 5
   63 
   64 patternProperties:
   65   "^[a-z0-9]+-[a-z0-9]+$":
   66     if:
   67       type: object
   68     then:
   69       description: |
   70         These are pad configuration nodes. On Tegra SoCs a pad is a set of
   71         pins which are configured as a group. The pin grouping is a fixed
   72         attribute of the hardware. The PMC can be used to set pad power
   73         state and signaling voltage. A pad can be either in active or
   74         power down mode. The support for power state and signaling voltage
   75         configuration varies depending on the pad in question. 3.3 V and
   76         1.8 V signaling voltages are supported on pins where software
   77         controllable signaling voltage switching is available.
   78 
   79         Pad configurations are described with pin configuration nodes
   80         which are placed under the pmc node and they are referred to by
   81         the pinctrl client properties. For more information see
   82 
   83           Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
   84 
   85         The following pads are present on Tegra186:
   86 
   87           csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
   88           pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
   89           hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
   90           dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
   91           sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
   92 
   93         The following pads are present on Tegra194:
   94 
   95           csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
   96           pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
   97           pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
   98           soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
   99           hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
  100           pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
  101           spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
  102           audio-hv, ao-hv
  103 
  104       properties:
  105         pins:
  106           $ref: /schemas/types.yaml#/definitions/string
  107           description: Must contain the name of the pad(s) to be
  108             configured.
  109 
  110         low-power-enable:
  111           description: Configure the pad into power down mode.
  112           $ref: /schemas/types.yaml#/definitions/flag
  113 
  114         low-power-disable:
  115           description: Configure the pad into active mode.
  116           $ref: /schemas/types.yaml#/definitions/flag
  117 
  118         power-source:
  119           $ref: /schemas/types.yaml#/definitions/uint32
  120           description: |
  121             Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
  122             TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
  123             voltages.
  124 
  125             The values are defined in
  126 
  127               include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
  128 
  129             The power state can be configured on all of the above pads
  130             except for ao-hv. Following pads have software configurable
  131             signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
  132             audio-hv, ao-hv.
  133 
  134         phandle: true
  135 
  136       required:
  137         - pins
  138 
  139       additionalProperties: false
  140 
  141 required:
  142   - compatible
  143   - reg
  144   - reg-names
  145 
  146 additionalProperties: false
  147 
  148 dependencies:
  149   interrupt-controller: ['#interrupt-cells']
  150   "#interrupt-cells":
  151     required:
  152       - interrupt-controller
  153 
  154 examples:
  155   - |
  156     #include <dt-bindings/clock/tegra186-clock.h>
  157     #include <dt-bindings/interrupt-controller/arm-gic.h>
  158     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
  159     #include <dt-bindings/memory/tegra186-mc.h>
  160     #include <dt-bindings/reset/tegra186-reset.h>
  161 
  162     pmc@c3600000 {
  163         compatible = "nvidia,tegra186-pmc";
  164         reg = <0x0c360000 0x10000>,
  165               <0x0c370000 0x10000>,
  166               <0x0c380000 0x10000>,
  167               <0x0c390000 0x10000>;
  168         reg-names = "pmc", "wake", "aotag", "scratch";
  169         nvidia,invert-interrupt;
  170 
  171         sdmmc1_3v3: sdmmc1-3v3 {
  172             pins = "sdmmc1-hv";
  173             power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
  174         };
  175 
  176         sdmmc1_1v8: sdmmc1-1v8 {
  177             pins = "sdmmc1-hv";
  178             power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
  179         };
  180     };
  181 
  182     sdmmc1: mmc@3400000 {
  183         compatible = "nvidia,tegra186-sdhci";
  184         reg = <0x03400000 0x10000>;
  185         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  186         clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
  187                  <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
  188         clock-names = "sdhci", "tmclk";
  189         resets = <&bpmp TEGRA186_RESET_SDMMC1>;
  190         reset-names = "sdhci";
  191         interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
  192                         <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
  193         interconnect-names = "dma-mem", "write";
  194         iommus = <&smmu TEGRA186_SID_SDMMC1>;
  195         pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
  196         pinctrl-0 = <&sdmmc1_3v3>;
  197         pinctrl-1 = <&sdmmc1_1v8>;
  198     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml

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sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra186-pmc.yaml