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sys/contrib/device-tree/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
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1 # SPDX-License-Identifier: GPL-2.0 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: Tegra Power Management Controller (PMC) 8 9 maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 12 13 properties: 14 compatible: 15 enum: 16 - nvidia,tegra20-pmc 17 - nvidia,tegra30-pmc 18 - nvidia,tegra114-pmc 19 - nvidia,tegra124-pmc 20 - nvidia,tegra210-pmc 21 22 reg: 23 maxItems: 1 24 description: 25 Offset and length of the register set for the device. 26 27 clock-names: 28 items: 29 - const: pclk 30 - const: clk32k_in 31 description: 32 Must includes entries pclk and clk32k_in. 33 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock 34 input to Tegra. 35 36 clocks: 37 maxItems: 2 38 description: 39 Must contain an entry for each entry in clock-names. 40 See ../clocks/clocks-bindings.txt for details. 41 42 '#clock-cells': 43 const: 1 44 description: 45 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. 46 PMC also has blink control which allows 32Khz clock output to 47 Tegra blink pad. 48 Consumer of PMC clock should specify the desired clock by having 49 the clock ID in its "clocks" phandle cell with pmc clock provider. 50 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC 51 clock IDs. 52 53 '#interrupt-cells': 54 const: 2 55 description: 56 Specifies number of cells needed to encode an interrupt source. 57 The value must be 2. 58 59 interrupt-controller: true 60 61 nvidia,invert-interrupt: 62 $ref: /schemas/types.yaml#/definitions/flag 63 description: Inverts the PMU interrupt signal. 64 The PMU is an external Power Management Unit, whose interrupt output 65 signal is fed into the PMC. This signal is optionally inverted, and 66 then fed into the ARM GIC. The PMC is not involved in the detection 67 or handling of this interrupt signal, merely its inversion. 68 69 nvidia,core-power-req-active-high: 70 $ref: /schemas/types.yaml#/definitions/flag 71 description: Core power request active-high. 72 73 nvidia,sys-clock-req-active-high: 74 $ref: /schemas/types.yaml#/definitions/flag 75 description: System clock request active-high. 76 77 nvidia,combined-power-req: 78 $ref: /schemas/types.yaml#/definitions/flag 79 description: combined power request for CPU and Core. 80 81 nvidia,cpu-pwr-good-en: 82 $ref: /schemas/types.yaml#/definitions/flag 83 description: 84 CPU power good signal from external PMIC to PMC is enabled. 85 86 nvidia,suspend-mode: 87 $ref: /schemas/types.yaml#/definitions/uint32 88 enum: [0, 1, 2] 89 description: 90 The suspend mode that the platform should use. 91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh 92 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh 93 Mode 2 is for LP2, CPU voltage off 94 95 nvidia,cpu-pwr-good-time: 96 $ref: /schemas/types.yaml#/definitions/uint32 97 description: CPU power good time in uSec. 98 99 nvidia,cpu-pwr-off-time: 100 $ref: /schemas/types.yaml#/definitions/uint32 101 description: CPU power off time in uSec. 102 103 nvidia,core-pwr-good-time: 104 $ref: /schemas/types.yaml#/definitions/uint32-array 105 description: 106 <Oscillator-stable-time Power-stable-time> 107 Core power good time in uSec. 108 109 nvidia,core-pwr-off-time: 110 $ref: /schemas/types.yaml#/definitions/uint32 111 description: Core power off time in uSec. 112 113 nvidia,lp0-vec: 114 $ref: /schemas/types.yaml#/definitions/uint32-array 115 description: 116 <start length> Starting address and length of LP0 vector. 117 The LP0 vector contains the warm boot code that is executed 118 by AVP when resuming from the LP0 state. 119 The AVP (Audio-Video Processor) is an ARM7 processor and 120 always being the first boot processor when chip is power on 121 or resume from deep sleep mode. When the system is resumed 122 from the deep sleep mode, the warm boot code will restore 123 some PLLs, clocks and then brings up CPU0 for resuming the 124 system. 125 126 i2c-thermtrip: 127 type: object 128 description: 129 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, 130 hardware-triggered thermal reset will be enabled. 131 132 properties: 133 nvidia,i2c-controller-id: 134 $ref: /schemas/types.yaml#/definitions/uint32 135 description: 136 ID of I2C controller to send poweroff command to PMU. 137 Valid values are described in section 9.2.148 138 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference 139 Manual. 140 141 nvidia,bus-addr: 142 $ref: /schemas/types.yaml#/definitions/uint32 143 description: Bus address of the PMU on the I2C bus. 144 145 nvidia,reg-addr: 146 $ref: /schemas/types.yaml#/definitions/uint32 147 description: PMU I2C register address to issue poweroff command. 148 149 nvidia,reg-data: 150 $ref: /schemas/types.yaml#/definitions/uint32 151 description: Poweroff command to write to PMU. 152 153 nvidia,pinmux-id: 154 $ref: /schemas/types.yaml#/definitions/uint32 155 description: 156 Pinmux used by the hardware when issuing Poweroff command. 157 Defaults to 0. Valid values are described in section 12.5.2 158 "Pinmux Support" of the Tegra4 Technical Reference Manual. 159 160 required: 161 - nvidia,i2c-controller-id 162 - nvidia,bus-addr 163 - nvidia,reg-addr 164 - nvidia,reg-data 165 166 additionalProperties: false 167 168 powergates: 169 type: object 170 description: | 171 This node contains a hierarchy of power domain nodes, which should 172 match the powergates on the Tegra SoC. Each powergate node 173 represents a power-domain on the Tegra SoC that can be power-gated 174 by the Tegra PMC. 175 Hardware blocks belonging to a power domain should contain 176 "power-domains" property that is a phandle pointing to corresponding 177 powergate node. 178 The name of the powergate node should be one of the below. Note that 179 not every powergate is applicable to all Tegra devices and the following 180 list shows which powergates are applicable to which devices. 181 Please refer to Tegra TRM for mode details on the powergate nodes to 182 use for each power-gate block inside Tegra. 183 Name Description Devices Applicable 184 3d 3D Graphics Tegra20/114/124/210 185 3d0 3D Graphics 0 Tegra30 186 3d1 3D Graphics 1 Tegra30 187 aud Audio Tegra210 188 dfd Debug Tegra210 189 dis Display A Tegra114/124/210 190 disb Display B Tegra114/124/210 191 heg 2D Graphics Tegra30/114/124/210 192 iram Internal RAM Tegra124/210 193 mpe MPEG Encode All 194 nvdec NVIDIA Video Decode Engine Tegra210 195 nvjpg NVIDIA JPEG Engine Tegra210 196 pcie PCIE Tegra20/30/124/210 197 sata SATA Tegra30/124/210 198 sor Display interfaces Tegra124/210 199 ve2 Video Encode Engine 2 Tegra210 200 venc Video Encode Engine All 201 vdec Video Decode Engine Tegra20/30/114/124 202 vic Video Imaging Compositor Tegra124/210 203 xusba USB Partition A Tegra114/124/210 204 xusbb USB Partition B Tegra114/124/210 205 xusbc USB Partition C Tegra114/124/210 206 207 patternProperties: 208 "^[a-z0-9]+$": 209 type: object 210 211 properties: 212 clocks: 213 minItems: 1 214 maxItems: 8 215 description: 216 Must contain an entry for each clock required by the PMC 217 for controlling a power-gate. 218 See ../clocks/clock-bindings.txt document for more details. 219 220 resets: 221 minItems: 1 222 maxItems: 8 223 description: 224 Must contain an entry for each reset required by the PMC 225 for controlling a power-gate. 226 See ../reset/reset.txt for more details. 227 228 '#power-domain-cells': 229 const: 0 230 description: Must be 0. 231 232 required: 233 - clocks 234 - resets 235 - '#power-domain-cells' 236 237 additionalProperties: false 238 239 patternProperties: 240 "^[a-f0-9]+-[a-f0-9]+$": 241 type: object 242 description: 243 This is a Pad configuration node. On Tegra SOCs a pad is a set of 244 pins which are configured as a group. The pin grouping is a fixed 245 attribute of the hardware. The PMC can be used to set pad power state 246 and signaling voltage. A pad can be either in active or power down mode. 247 The support for power state and signaling voltage configuration varies 248 depending on the pad in question. 3.3V and 1.8V signaling voltages 249 are supported on pins where software controllable signaling voltage 250 switching is available. 251 252 The pad configuration state nodes are placed under the pmc node and they 253 are referred to by the pinctrl client properties. For more information 254 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. 255 The pad name should be used as the value of the pins property in pin 256 configuration nodes. 257 258 The following pads are present on Tegra124 and Tegra132 259 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, 260 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 261 sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. 262 263 The following pads are present on Tegra210 264 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, 265 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, 266 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 267 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. 268 269 properties: 270 pins: 271 $ref: /schemas/types.yaml#/definitions/string 272 description: Must contain name of the pad(s) to be configured. 273 274 low-power-enable: 275 $ref: /schemas/types.yaml#/definitions/flag 276 description: Configure the pad into power down mode. 277 278 low-power-disable: 279 $ref: /schemas/types.yaml#/definitions/flag 280 description: Configure the pad into active mode. 281 282 power-source: 283 $ref: /schemas/types.yaml#/definitions/uint32 284 description: 285 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 286 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. 287 The values are defined in 288 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. 289 Power state can be configured on all Tegra124 and Tegra132 290 pads. None of the Tegra124 or Tegra132 pads support signaling 291 voltage switching. 292 All of the listed Tegra210 pads except pex-cntrl support power 293 state configuration. Signaling voltage switching is supported 294 on below Tegra210 pads. 295 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, 296 sdmmc3, spi, spi-hv, and uart. 297 298 required: 299 - pins 300 301 additionalProperties: false 302 303 core-domain: 304 type: object 305 description: | 306 The vast majority of hardware blocks of Tegra SoC belong to a 307 Core power domain, which has a dedicated voltage rail that powers 308 the blocks. 309 310 properties: 311 operating-points-v2: 312 description: 313 Should contain level, voltages and opp-supported-hw property. 314 The supported-hw is a bitfield indicating SoC speedo or process 315 ID mask. 316 317 "#power-domain-cells": 318 const: 0 319 320 required: 321 - operating-points-v2 322 - "#power-domain-cells" 323 324 additionalProperties: false 325 326 core-supply: 327 description: 328 Phandle to voltage regulator connected to the SoC Core power rail. 329 330 required: 331 - compatible 332 - reg 333 - clock-names 334 - clocks 335 - '#clock-cells' 336 337 additionalProperties: false 338 339 dependencies: 340 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] 341 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] 342 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] 343 344 examples: 345 - | 346 347 #include <dt-bindings/clock/tegra210-car.h> 348 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 349 #include <dt-bindings/soc/tegra-pmc.h> 350 351 tegra_pmc: pmc@7000e400 { 352 compatible = "nvidia,tegra210-pmc"; 353 reg = <0x7000e400 0x400>; 354 core-supply = <®ulator>; 355 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 356 clock-names = "pclk", "clk32k_in"; 357 #clock-cells = <1>; 358 359 nvidia,invert-interrupt; 360 nvidia,suspend-mode = <0>; 361 nvidia,cpu-pwr-good-time = <0>; 362 nvidia,cpu-pwr-off-time = <0>; 363 nvidia,core-pwr-good-time = <4587 3876>; 364 nvidia,core-pwr-off-time = <39065>; 365 nvidia,core-power-req-active-high; 366 nvidia,sys-clock-req-active-high; 367 368 pd_core: core-domain { 369 operating-points-v2 = <&core_opp_table>; 370 #power-domain-cells = <0>; 371 }; 372 373 powergates { 374 pd_audio: aud { 375 clocks = <&tegra_car TEGRA210_CLK_APE>, 376 <&tegra_car TEGRA210_CLK_APB2APE>; 377 resets = <&tegra_car 198>; 378 power-domains = <&pd_core>; 379 #power-domain-cells = <0>; 380 }; 381 382 pd_xusbss: xusba { 383 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 384 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 385 power-domains = <&pd_core>; 386 #power-domain-cells = <0>; 387 }; 388 }; 389 };
Cache object: e77df73375af74eb18ed9b2b32c60b27
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