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     1 Broadcom GISB bus Arbiter controller
    2 
    3 Required properties:
    4 
    5 - compatible:
    6     "brcm,bcm7278-gisb-arb" for V7 28nm chips
    7     "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
    8     "brcm,bcm7435-gisb-arb" for newer 40nm chips
    9     "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
   10     "brcm,bcm7038-gisb-arb" for 130nm chips
   11 - reg: specifies the base physical address and size of the registers
   12 - interrupts: specifies the two interrupts (timeout and TEA) to be used from
   13   the parent interrupt controller. A third optional interrupt may be specified
   14   for breakpoints.
   15 
   16 Optional properties:
   17 
   18 - brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
   19   masters are valid at the system level
   20 - brcm,gisb-arb-master-names: string list of the litteral name of the GISB
   21   masters. Should match the number of bits set in brcm,gisb-master-mask and
   22   the order in which they appear
   23 
   24 Example:
   25 
   26 gisb-arb@f0400000 {
   27         compatible = "brcm,gisb-arb";
   28         reg = <0xf0400000 0x800>;
   29         interrupts = <0>, <2>;
   30         interrupt-parent = <&sun_l2_intc>;
   31 
   32         brcm,gisb-arb-master-mask = <0x7>;
   33         brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
   34 };
Cache object: d7db98492603284a7b98fc704c824846 
 
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