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     1 NVIDIA Tegra ACONNECT Bus
    2 
    3 The Tegra ACONNECT bus is an AXI switch which is used to connnect various
    4 components inside the Audio Processing Engine (APE). All CPU accesses to
    5 the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
    6 
    7 Required properties:
    8 - compatible: Must be "nvidia,tegra210-aconnect".
    9 - clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
   10   and APE interface clock (TEGRA210_CLK_APB2APE).
   11 - clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
   12   'clocks' entries.
   13 - power-domains: Must contain a phandle that points to the audio powergate
   14   (namely 'aud') for Tegra210.
   15 - #address-cells: The number of cells used to represent physical base addresses
   16   in the aconnect address space. Should be 1.
   17 - #size-cells: The number of cells used to represent the size of an address
   18   range in the aconnect address space. Should be 1.
   19 - ranges: Mapping of the aconnect address space to the CPU address space.
   20 
   21 All devices accessed via the ACONNNECT are described by child-nodes.
   22 
   23 Example:
   24 
   25         aconnect@702c0000 {
   26                 compatible = "nvidia,tegra210-aconnect";
   27                 clocks = <&tegra_car TEGRA210_CLK_APE>,
   28                          <&tegra_car TEGRA210_CLK_APB2APE>;
   29                 clock-names = "ape", "apb2ape";
   30                 power-domains = <&pd_audio>;
   31 
   32                 #address-cells = <1>;
   33                 #size-cells = <1>;
   34                 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
   35 
   36 
   37                 child1 {
   38                         ...
   39                 };
   40 
   41                 child2 {
   42                         ...
   43                 };
   44         };
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