ti-sysc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Texas Instruments interconnect target module binding
    8 
    9 maintainers:
   10   - Tony Lindgren <tony@atomide.com>
   11 
   12 description:
   13   Texas Instruments SoCs can have a generic interconnect target module
   14   for devices connected to various interconnects such as L3 interconnect
   15   using Arteris NoC, and L4 interconnect using Sonics s3220. This module
   16   is mostly used for interaction between module and Power, Reset and Clock
   17   Manager PRCM. It participates in the OCP Disconnect Protocol, but other
   18   than that it is mostly independent of the interconnect.
   19 
   20   Each interconnect target module can have one or more devices connected to
   21   it. There is a set of control registers for managing the interconnect target
   22   module clocks, idle modes and interconnect level resets.
   23 
   24   The interconnect target module control registers are sprinkled into the
   25   unused register address space of the first child device IP block managed by
   26   the interconnect target module. Typically the register names are REVISION,
   27   SYSCONFIG and SYSSTATUS.
   28 
   29 properties:
   30   $nodename:
   31     pattern: "^target-module(@[0-9a-f]+)?$"
   32 
   33   compatible:
   34     oneOf:
   35       - items:
   36           - enum:
   37               - ti,sysc-omap2
   38               - ti,sysc-omap4
   39               - ti,sysc-omap4-simple
   40               - ti,sysc-omap2-timer
   41               - ti,sysc-omap4-timer
   42               - ti,sysc-omap3430-sr
   43               - ti,sysc-omap3630-sr
   44               - ti,sysc-omap4-sr
   45               - ti,sysc-omap3-sham
   46               - ti,sysc-omap-aes
   47               - ti,sysc-mcasp
   48               - ti,sysc-dra7-mcasp
   49               - ti,sysc-usb-host-fs
   50               - ti,sysc-dra7-mcan
   51               - ti,sysc-pruss
   52           - const: ti,sysc
   53       - items:
   54           - const: ti,sysc
   55 
   56   reg:
   57     description:
   58       Interconnect target module control registers consisting of
   59       REVISION, SYSCONFIG and SYSSTATUS registers as defined in the
   60       Technical Reference Manual for the SoC.
   61     minItems: 1
   62     maxItems: 3
   63 
   64   reg-names:
   65     description:
   66       Interconnect target module control register names consisting
   67       of "rev", "sysc" and "syss".
   68     oneOf:
   69       - minItems: 1
   70         items:
   71           - const: rev
   72           - const: sysc
   73           - const: syss
   74       - items:
   75           - const: rev
   76           - const: syss
   77       - enum: [ sysc, syss ]
   78 
   79   power-domains:
   80     description: Target module power domain if available.
   81     maxItems: 1
   82 
   83   clocks:
   84     description:
   85       Target module clocks consisting of one functional clock, one
   86       interface clock, and up to 8 module specific optional clocks.
   87       Some modules may have only the functional clock, and some have
   88       no configurable clocks.
   89     minItems: 1
   90     maxItems: 4
   91 
   92   clock-names:
   93     description:
   94       Target module clock names like "fck", "ick", "optck1", "optck2"
   95       if the clocks are configurable.
   96     oneOf:
   97       - enum: [ ick, fck, sys_clk ]
   98       - items:
   99           - const: fck
  100           - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
  101       - items:
  102           - const: fck
  103           - const: phy-clk
  104           - const: phy-clk-div
  105       - items:
  106           - const: fck
  107           - const: hdmi_clk
  108           - const: sys_clk
  109           - const: tv_clk
  110       - items:
  111           - const: fck
  112           - const: ahclkx
  113           - const: ahclkr
  114 
  115   resets:
  116     description:
  117       Target module reset bit in the RSTCTRL register if wired for the module.
  118       Note that the other reset bits should be mapped for the child device
  119       driver to use.
  120     maxItems: 1
  121 
  122   reset-names:
  123     description:
  124       Target module reset names in the RSTCTRL register, typically named
  125       "rstctrl" if only one reset bit is wired for the module.
  126     items:
  127       - const: rstctrl
  128 
  129   '#address-cells':
  130     enum: [ 1, 2 ]
  131 
  132   '#size-cells':
  133     enum: [ 1, 2 ]
  134 
  135   ranges: true
  136 
  137   dma-ranges: true
  138 
  139   ti,sysc-mask:
  140     description: Mask of supported register bits for the SYSCONFIG register
  141     $ref: /schemas/types.yaml#/definitions/uint32
  142 
  143   ti,sysc-midle:
  144     description: List of hardware supported idle modes
  145     $ref: /schemas/types.yaml#/definitions/uint32-array
  146 
  147   ti,sysc-sidle:
  148     description: List of hardware supported idle modes
  149     $ref: /schemas/types.yaml#/definitions/uint32-array
  150 
  151   ti,syss-mask:
  152     description: Mask of supported register bits for the SYSSTATUS register
  153     $ref: /schemas/types.yaml#/definitions/uint32
  154 
  155   ti,sysc-delay-us:
  156     description: Delay needed after OCP softreset before accessing SYCONFIG
  157     default: 0
  158     minimum: 0
  159     maximum: 2
  160 
  161   ti,no-reset-on-init:
  162     description: Interconnect target module shall not be reset at init
  163     type: boolean
  164 
  165   ti,no-idle-on-init:
  166     description: Interconnect target module shall not be idled at init
  167     type: boolean
  168 
  169   ti,no-idle:
  170     description: Interconnect target module shall not be idled
  171     type: boolean
  172 
  173   ti,hwmods:
  174     description: Interconnect module name to use with legacy hwmod data
  175     $ref: /schemas/types.yaml#/definitions/string
  176     deprecated: true
  177 
  178 required:
  179   - compatible
  180   - '#address-cells'
  181   - '#size-cells'
  182   - ranges
  183 
  184 additionalProperties:
  185   type: object
  186 
  187 examples:
  188   - |
  189     #include <dt-bindings/bus/ti-sysc.h>
  190     #include <dt-bindings/clock/omap4.h>
  191 
  192     target-module@2b000 {
  193         compatible = "ti,sysc-omap2", "ti,sysc";
  194         ti,hwmods = "usb_otg_hs";
  195         reg = <0x2b400 0x4>,
  196               <0x2b404 0x4>,
  197               <0x2b408 0x4>;
  198         reg-names = "rev", "sysc", "syss";
  199         clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
  200         clock-names = "fck";
  201         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  202                          SYSC_OMAP2_SOFTRESET |
  203                          SYSC_OMAP2_AUTOIDLE)>;
  204         ti,sysc-midle = <SYSC_IDLE_FORCE>,
  205                         <SYSC_IDLE_NO>,
  206                         <SYSC_IDLE_SMART>;
  207         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  208                         <SYSC_IDLE_NO>,
  209                         <SYSC_IDLE_SMART>,
  210                         <SYSC_IDLE_SMART_WKUP>;
  211         ti,syss-mask = <1>;
  212         #address-cells = <1>;
  213         #size-cells = <1>;
  214         ranges = <0 0x2b000 0x1000>;
  215     };

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