| 
     1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Microchip LAN966X Generic Clock Controller
    8 
    9 maintainers:
   10   - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
   11 
   12 description: |
   13   The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
   14   ddr_clk and sys_clk. This clock controller generates and supplies
   15   clock to various peripherals within the SoC.
   16 
   17 properties:
   18   compatible:
   19     const: microchip,lan966x-gck
   20 
   21   reg:
   22     minItems: 1
   23     items:
   24       - description: Generic clock registers
   25       - description: Optional gate clock registers
   26 
   27   clocks:
   28     items:
   29       - description: CPU clock source
   30       - description: DDR clock source
   31       - description: System clock source
   32 
   33   clock-names:
   34     items:
   35       - const: cpu
   36       - const: ddr
   37       - const: sys
   38 
   39   '#clock-cells':
   40     const: 1
   41 
   42 required:
   43   - compatible
   44   - reg
   45   - clocks
   46   - clock-names
   47   - '#clock-cells'
   48 
   49 additionalProperties: false
   50 
   51 examples:
   52   - |
   53     clks: clock-controller@e00c00a8 {
   54         compatible = "microchip,lan966x-gck";
   55         #clock-cells = <1>;
   56         clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
   57         clock-names = "cpu", "ddr", "sys";
   58         reg = <0xe00c00a8 0x38>;
   59     };
   60 ...
Cache object: 2ae73292c2d63380dba01a7dacd95b07 
 
 |