| 
     1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
    2 
    3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
    4 
    5 Required Properties:
    6 - compatible: has to be "qca,<soctype>-pll" and one of the following
    7   fallbacks:
    8   - "qca,ar7100-pll"
    9   - "qca,ar7240-pll"
   10   - "qca,ar9130-pll"
   11   - "qca,ar9330-pll"
   12   - "qca,ar9340-pll"
   13   - "qca,qca9550-pll"
   14 - reg: Base address and size of the controllers memory area
   15 - clock-names: Name of the input clock, has to be "ref"
   16 - clocks: phandle of the external reference clock
   17 - #clock-cells: has to be one
   18 
   19 Optional properties:
   20 - clock-output-names: should be "cpu", "ddr", "ahb"
   21 
   22 Example:
   23 
   24         pll-controller@18050000 {
   25                 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
   26                 reg = <0x18050000 0x20>;
   27 
   28                 clock-names = "ref";
   29                 clocks = <&extosc>;
   30 
   31                 #clock-cells = <1>;
   32                 clock-output-names = "cpu", "ddr", "ahb";
   33         };
Cache object: f22a9fb43812dc5f504d3ec6862167b8 
 
 |