qcom,dispcc-sm6350.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Display Clock & Reset Controller Binding for SM6350
    8 
    9 maintainers:
   10   - Konrad Dybcio <konrad.dybcio@somainline.org>
   11 
   12 description: |
   13   Qualcomm display clock control module which supports the clocks, resets and
   14   power domains on SM6350.
   15 
   16   See also dt-bindings/clock/qcom,dispcc-sm6350.h.
   17 
   18 properties:
   19   compatible:
   20     const: qcom,sm6350-dispcc
   21 
   22   clocks:
   23     items:
   24       - description: Board XO source
   25       - description: GPLL0 source from GCC
   26       - description: Byte clock from DSI PHY
   27       - description: Pixel clock from DSI PHY
   28       - description: Link clock from DP PHY
   29       - description: VCO DIV clock from DP PHY
   30 
   31   clock-names:
   32     items:
   33       - const: bi_tcxo
   34       - const: gcc_disp_gpll0_clk
   35       - const: dsi0_phy_pll_out_byteclk
   36       - const: dsi0_phy_pll_out_dsiclk
   37       - const: dp_phy_pll_link_clk
   38       - const: dp_phy_pll_vco_div_clk
   39 
   40   '#clock-cells':
   41     const: 1
   42 
   43   '#reset-cells':
   44     const: 1
   45 
   46   '#power-domain-cells':
   47     const: 1
   48 
   49   reg:
   50     maxItems: 1
   51 
   52 required:
   53   - compatible
   54   - reg
   55   - clocks
   56   - clock-names
   57   - '#clock-cells'
   58   - '#reset-cells'
   59   - '#power-domain-cells'
   60 
   61 additionalProperties: false
   62 
   63 examples:
   64   - |
   65     #include <dt-bindings/clock/qcom,gcc-sm6350.h>
   66     #include <dt-bindings/clock/qcom,rpmh.h>
   67     clock-controller@af00000 {
   68       compatible = "qcom,sm6350-dispcc";
   69       reg = <0x0af00000 0x20000>;
   70       clocks = <&rpmhcc RPMH_CXO_CLK>,
   71                <&gcc GCC_DISP_GPLL0_CLK>,
   72                <&dsi_phy 0>,
   73                <&dsi_phy 1>,
   74                <&dp_phy 0>,
   75                <&dp_phy 1>;
   76       clock-names = "bi_tcxo",
   77                     "gcc_disp_gpll0_clk",
   78                     "dsi0_phy_pll_out_byteclk",
   79                     "dsi0_phy_pll_out_dsiclk",
   80                     "dp_phy_pll_link_clk",
   81                     "dp_phy_pll_vco_div_clk";
   82       #clock-cells = <1>;
   83       #reset-cells = <1>;
   84       #power-domain-cells = <1>;
   85     };
   86 ...

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sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6350.yaml