1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
8
9 maintainers:
10 - Taniya Das <tdas@codeaurora.org>
11
12 description: |
13 Qualcomm graphics clock control module which supports the clocks, resets and
14 power domains on MSM8998.
15
16 See also dt-bindings/clock/qcom,gpucc-msm8998.h.
17
18 properties:
19 compatible:
20 const: qcom,msm8998-gpucc
21
22 clocks:
23 items:
24 - description: Board XO source
25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
26
27 clock-names:
28 items:
29 - const: xo
30 - const: gpll0
31
32 '#clock-cells':
33 const: 1
34
35 '#reset-cells':
36 const: 1
37
38 '#power-domain-cells':
39 const: 1
40
41 reg:
42 maxItems: 1
43
44 required:
45 - compatible
46 - reg
47 - clocks
48 - clock-names
49 - '#clock-cells'
50 - '#reset-cells'
51 - '#power-domain-cells'
52
53 additionalProperties: false
54
55 examples:
56 - |
57 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
58 #include <dt-bindings/clock/qcom,rpmcc.h>
59 clock-controller@5065000 {
60 compatible = "qcom,msm8998-gpucc";
61 #clock-cells = <1>;
62 #reset-cells = <1>;
63 #power-domain-cells = <1>;
64 reg = <0x05065000 0x9000>;
65 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>;
66 clock-names = "xo", "gpll0";
67 };
68 ...
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