qcom,sc7280-dispcc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Display Clock & Reset Controller Binding for SC7280
    8 
    9 maintainers:
   10   - Taniya Das <tdas@codeaurora.org>
   11 
   12 description: |
   13   Qualcomm display clock control module which supports the clocks, resets and
   14   power domains on SC7280.
   15 
   16   See also dt-bindings/clock/qcom,dispcc-sc7280.h.
   17 
   18 properties:
   19   compatible:
   20     const: qcom,sc7280-dispcc
   21 
   22   clocks:
   23     items:
   24       - description: Board XO source
   25       - description: GPLL0 source from GCC
   26       - description: Byte clock from DSI PHY
   27       - description: Pixel clock from DSI PHY
   28       - description: Link clock from DP PHY
   29       - description: VCO DIV clock from DP PHY
   30       - description: Link clock from EDP PHY
   31       - description: VCO DIV clock from EDP PHY
   32 
   33   clock-names:
   34     items:
   35       - const: bi_tcxo
   36       - const: gcc_disp_gpll0_clk
   37       - const: dsi0_phy_pll_out_byteclk
   38       - const: dsi0_phy_pll_out_dsiclk
   39       - const: dp_phy_pll_link_clk
   40       - const: dp_phy_pll_vco_div_clk
   41       - const: edp_phy_pll_link_clk
   42       - const: edp_phy_pll_vco_div_clk
   43 
   44   '#clock-cells':
   45     const: 1
   46 
   47   '#reset-cells':
   48     const: 1
   49 
   50   '#power-domain-cells':
   51     const: 1
   52 
   53   reg:
   54     maxItems: 1
   55 
   56 required:
   57   - compatible
   58   - reg
   59   - clocks
   60   - clock-names
   61   - '#clock-cells'
   62   - '#reset-cells'
   63   - '#power-domain-cells'
   64 
   65 additionalProperties: false
   66 
   67 examples:
   68   - |
   69     #include <dt-bindings/clock/qcom,gcc-sc7280.h>
   70     #include <dt-bindings/clock/qcom,rpmh.h>
   71     clock-controller@af00000 {
   72       compatible = "qcom,sc7280-dispcc";
   73       reg = <0x0af00000 0x200000>;
   74       clocks = <&rpmhcc RPMH_CXO_CLK>,
   75                <&gcc GCC_DISP_GPLL0_CLK_SRC>,
   76                <&dsi_phy 0>,
   77                <&dsi_phy 1>,
   78                <&dp_phy 0>,
   79                <&dp_phy 1>,
   80                <&edp_phy 0>,
   81                <&edp_phy 1>;
   82       clock-names = "bi_tcxo",
   83                     "gcc_disp_gpll0_clk",
   84                     "dsi0_phy_pll_out_byteclk",
   85                     "dsi0_phy_pll_out_dsiclk",
   86                     "dp_phy_pll_link_clk",
   87                     "dp_phy_pll_vco_div_clk",
   88                     "edp_phy_pll_link_clk",
   89                     "edp_phy_pll_vco_div_clk";
   90       #clock-cells = <1>;
   91       #reset-cells = <1>;
   92       #power-domain-cells = <1>;
   93     };
   94 ...

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sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml