qcom,sdm845-dispcc.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
    8 
    9 maintainers:
   10   - Taniya Das <tdas@codeaurora.org>
   11 
   12 description: |
   13   Qualcomm display clock control module which supports the clocks, resets and
   14   power domains on SDM845.
   15 
   16   See also dt-bindings/clock/qcom,dispcc-sdm845.h.
   17 
   18 properties:
   19   compatible:
   20     const: qcom,sdm845-dispcc
   21 
   22   # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
   23   # The code had to use hardcoded mechanisms to find the input clocks.
   24   # New dts files should have these clocks.
   25   clocks:
   26     items:
   27       - description: Board XO source
   28       - description: GPLL0 source from GCC
   29       - description: GPLL0 div source from GCC
   30       - description: Byte clock from DSI PHY0
   31       - description: Pixel clock from DSI PHY0
   32       - description: Byte clock from DSI PHY1
   33       - description: Pixel clock from DSI PHY1
   34       - description: Link clock from DP PHY
   35       - description: VCO DIV clock from DP PHY
   36 
   37   clock-names:
   38     items:
   39       - const: bi_tcxo
   40       - const: gcc_disp_gpll0_clk_src
   41       - const: gcc_disp_gpll0_div_clk_src
   42       - const: dsi0_phy_pll_out_byteclk
   43       - const: dsi0_phy_pll_out_dsiclk
   44       - const: dsi1_phy_pll_out_byteclk
   45       - const: dsi1_phy_pll_out_dsiclk
   46       - const: dp_link_clk_divsel_ten
   47       - const: dp_vco_divided_clk_src_mux
   48 
   49   '#clock-cells':
   50     const: 1
   51 
   52   '#reset-cells':
   53     const: 1
   54 
   55   '#power-domain-cells':
   56     const: 1
   57 
   58   reg:
   59     maxItems: 1
   60 
   61 required:
   62   - compatible
   63   - reg
   64   - clocks
   65   - clock-names
   66   - '#clock-cells'
   67   - '#reset-cells'
   68   - '#power-domain-cells'
   69 
   70 additionalProperties: false
   71 
   72 examples:
   73   - |
   74     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
   75     #include <dt-bindings/clock/qcom,rpmh.h>
   76     clock-controller@af00000 {
   77       compatible = "qcom,sdm845-dispcc";
   78       reg = <0x0af00000 0x10000>;
   79       clocks = <&rpmhcc RPMH_CXO_CLK>,
   80                <&gcc GCC_DISP_GPLL0_CLK_SRC>,
   81                <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
   82                <&dsi0_phy 0>,
   83                <&dsi0_phy 1>,
   84                <&dsi1_phy 0>,
   85                <&dsi1_phy 1>,
   86                <&dp_phy 0>,
   87                <&dp_phy 1>;
   88       clock-names = "bi_tcxo",
   89                     "gcc_disp_gpll0_clk_src",
   90                     "gcc_disp_gpll0_div_clk_src",
   91                     "dsi0_phy_pll_out_byteclk",
   92                     "dsi0_phy_pll_out_dsiclk",
   93                     "dsi1_phy_pll_out_byteclk",
   94                     "dsi1_phy_pll_out_dsiclk",
   95                     "dp_link_clk_divsel_ten",
   96                     "dp_vco_divided_clk_src_mux";
   97       #clock-cells = <1>;
   98       #reset-cells = <1>;
   99       #power-domain-cells = <1>;
  100     };
  101 ...

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sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml