FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/clock/rockchip,rk3036-cru.txt

     * Rockchip RK3036 Clock and Reset Unit
     
     The RK3036 clock controller generates and supplies clock to various
     controllers within the SoC and also implements a reset controller for SoC
     peripherals.
     
     Required Properties:
     
     - compatible: should be "rockchip,rk3036-cru"
    - reg: physical base address of the controller and length of memory mapped
      region.
    - #clock-cells: should be 1.
    - #reset-cells: should be 1.
    
    Optional Properties:
    
    - rockchip,grf: phandle to the syscon managing the "general register files"
      If missing pll rates are not changeable, due to the missing pll lock status.
    
    Each clock is assigned an identifier and client nodes can use this identifier
    to specify the clock which they consume. All available clocks are defined as
    preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
    used in device tree sources. Similar macros exist for the reset sources in
    these files.
    
    External clocks:
    
    There are several clocks that are generated outside the SoC. It is expected
    that they are defined using standard clock bindings with following
    clock-output-names:
     - "xin24m" - crystal input - required,
     - "ext_i2s" - external I2S clock - optional,
     - "rmii_clkin" - external EMAC clock - optional
    
    Example: Clock controller node:
    
            cru: cru@20000000 {
                    compatible = "rockchip,rk3036-cru";
                    reg = <0x20000000 0x1000>;
                    rockchip,grf = <&grf>;
    
                    #clock-cells = <1>;
                    #reset-cells = <1>;
            };
    
    Example: UART controller node that consumes the clock generated by the clock
      controller:
    
            uart0: serial@20060000 {
                    compatible = "snps,dw-apb-uart";
                    reg = <0x20060000 0x100>;
                    interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                    reg-shift = <2>;
                    reg-io-width = <4>;
                    clocks = <&cru SCLK_UART0>;
            };

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