FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/clock/rockchip,rk3308-cru.yaml

     # SPDX-License-Identifier: GPL-2.0
     %YAML 1.2
     ---
     $id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
     $schema: http://devicetree.org/meta-schemas/core.yaml#
     
     title: Rockchip RK3308 Clock and Reset Unit (CRU)
     
     maintainers:
      - Elaine Zhang <zhangqing@rock-chips.com>
      - Heiko Stuebner <heiko@sntech.de>
    
    description: |
      The RK3308 clock controller generates and supplies clocks to various
      controllers within the SoC and also implements a reset controller for SoC
      peripherals.
      Each clock is assigned an identifier and client nodes can use this identifier
      to specify the clock which they consume. All available clocks are defined as
      preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
      used in device tree sources. Similar macros exist for the reset sources in
      these files.
      There are several clocks that are generated outside the SoC. It is expected
      that they are defined using standard clock bindings with following
      clock-output-names:
        - "xin24m"                               - crystal input      - required
        - "xin32k"                               - rtc clock          - optional
        - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
          "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
          "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
                                                   SPDIF clock        - optional
        - "mac_clkin"                            - external MAC clock - optional
    
    properties:
      compatible:
        enum:
          - rockchip,rk3308-cru
    
      reg:
        maxItems: 1
    
      "#clock-cells":
        const: 1
    
      "#reset-cells":
        const: 1
    
      clocks:
        maxItems: 1
    
      clock-names:
        const: xin24m
    
      rockchip,grf:
        $ref: /schemas/types.yaml#/definitions/phandle
        description:
          Phandle to the syscon managing the "general register files" (GRF),
          if missing pll rates are not changeable, due to the missing pll
          lock status.
    
    required:
      - compatible
      - reg
      - "#clock-cells"
      - "#reset-cells"
    
    additionalProperties: false
    
    examples:
      - |
        cru: clock-controller@ff500000 {
          compatible = "rockchip,rk3308-cru";
          reg = <0xff500000 0x1000>;
          rockchip,grf = <&grf>;
          #clock-cells = <1>;
          #reset-cells = <1>;
        };

Cache object: 5feef4a028472712d69288498526b6ec