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     1 Binding for a ST pll clock driver.
    2 
    3 This binding uses the common clock binding[1].
    4 Base address is located to the parent node. See clock binding[2]
    5 
    6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
    7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
    8 
    9 Required properties:
   10 
   11 - compatible : shall be:
   12         "st,clkgen-pll0"
   13         "st,clkgen-pll0-a0"
   14         "st,clkgen-pll0-c0"
   15         "st,clkgen-pll1"
   16         "st,clkgen-pll1-c0"
   17         "st,stih407-clkgen-plla9"
   18         "st,stih418-clkgen-plla9"
   19 
   20 - #clock-cells : From common clock binding; shall be set to 1.
   21 
   22 - clocks : From common clock binding
   23 
   24 - clock-output-names : From common clock binding.
   25 
   26 Example:
   27 
   28         clockgen-a9@92b0000 {
   29                 compatible = "st,clkgen-c32";
   30                 reg = <0x92b0000 0xffff>;
   31 
   32                 clockgen_a9_pll: clockgen-a9-pll {
   33                         #clock-cells = <1>;
   34                         compatible = "st,stih407-clkgen-plla9";
   35 
   36                         clocks = <&clk_sysin>;
   37 
   38                         clock-output-names = "clockgen-a9-pll-odf";
   39                 };
   40         };
Cache object: c89779f742f8ef8290cb32e4b080215f 
 
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