FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/clock/xlnx,zynqmp-clk.txt

     --------------------------------------------------------------------------
     Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
     Zynq MPSoC firmware interface
     --------------------------------------------------------------------------
     The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
     tree. It reads required input clock frequencies from the devicetree and acts
     as clock provider for all clock consumers of PS clocks.
     
     See clock_bindings.txt for more information on the generic clock bindings.
    
    Required properties:
     - #clock-cells:        Must be 1
     - compatible:          Must contain:   "xlnx,zynqmp-clk"
     - clocks:              List of clock specifiers which are external input
                            clocks to the given clock controller. Please refer
                            the next section to find the input clocks for a
                            given controller.
     - clock-names:         List of clock names which are exteral input clocks
                            to the given clock controller. Please refer to the
                            clock bindings for more details.
    
    Input clocks for zynqmp Ultrascale+ clock controller:
    
    The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
    inputs. These required clock inputs are:
     - pss_ref_clk (PS reference clock)
     - video_clk (reference clock for video system )
     - pss_alt_ref_clk (alternative PS reference clock)
     - aux_ref_clk
     - gt_crx_ref_clk (transceiver reference clock)
    
    The following strings are optional parameters to the 'clock-names' property in
    order to provide an optional (E)MIO clock source:
     - swdt0_ext_clk
     - swdt1_ext_clk
     - gem0_emio_clk
     - gem1_emio_clk
     - gem2_emio_clk
     - gem3_emio_clk
     - mio_clk_XX           # with XX = 00..77
     - mio_clk_50_or_51     #for the mux clock to gem tsu from 50 or 51
    
    
    Output clocks are registered based on clock information received
    from firmware. Output clocks indexes are mentioned in
    include/dt-bindings/clock/xlnx-zynqmp-clk.h.
    
    -------
    Example
    -------
    
    firmware {
            zynqmp_firmware: zynqmp-firmware {
                    compatible = "xlnx,zynqmp-firmware";
                    method = "smc";
                    zynqmp_clk: clock-controller {
                            #clock-cells = <1>;
                            compatible = "xlnx,zynqmp-clk";
                            clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
                            clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
                    };
            };
    };

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