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     1 Tegra124 CPU frequency scaling driver bindings
    2 ----------------------------------------------
    3 
    4 Both required and optional properties listed below must be defined
    5 under node /cpus/cpu@0.
    6 
    7 Required properties:
    8 - clocks: Must contain an entry for each entry in clock-names.
    9   See ../clocks/clock-bindings.txt for details.
   10 - clock-names: Must include the following entries:
   11   - cpu_g: Clock mux for the fast CPU cluster.
   12   - pll_x: Fast PLL clocksource.
   13   - pll_p: Auxiliary PLL used during fast PLL rate changes.
   14   - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
   15 
   16 Optional properties:
   17 - clock-latency: Specify the possible maximum transition latency for clock,
   18   in unit of nanoseconds.
   19 
   20 Example:
   21 --------
   22 cpus {
   23         #address-cells = <1>;
   24         #size-cells = <0>;
   25 
   26         cpu@0 {
   27                 device_type = "cpu";
   28                 compatible = "arm,cortex-a15";
   29                 reg = <0>;
   30 
   31                 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
   32                          <&tegra_car TEGRA124_CLK_PLL_X>,
   33                          <&tegra_car TEGRA124_CLK_PLL_P>,
   34                          <&dfll>;
   35                 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
   36                 clock-latency = <300000>;
   37         };
   38 
   39         <...>
   40 };
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