Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/crypto/fsl-sec4.txt
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1 ===================================================================== 2 SEC 4 Device Tree Binding 3 Copyright (C) 2008-2011 Freescale Semiconductor Inc. 4 5 CONTENTS 6 -Overview 7 -SEC 4 Node 8 -Job Ring Node 9 -Run Time Integrity Check (RTIC) Node 10 -Run Time Integrity Check (RTIC) Memory Node 11 -Secure Non-Volatile Storage (SNVS) Node 12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node 13 -Full Example 14 15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator 16 Accelerator and Assurance Module (CAAM). 17 18 ===================================================================== 19 Overview 20 21 DESCRIPTION 22 23 SEC 4 h/w can process requests from 2 types of sources. 24 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). 25 2. Job Rings (HW interface between cores & SEC 4 registers). 26 27 High Speed Data Path Configuration: 28 29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts 30 such as the P4080. The number of simultaneous dequeues the QI can make is 31 equal to the number of Descriptor Controller (DECO) engines in a particular 32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus 33 dequeue from 5 subportals simultaneously. 34 35 Job Ring Data Path Configuration: 36 37 Each JR is located on a separate 4k page, they may (or may not) be made visible 38 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so 39 up to 4 JRs can be configured; and all 4 JRs process requests in parallel. 40 41 ===================================================================== 42 SEC 4 Node 43 44 Description 45 46 Node defines the base address of the SEC 4 block. 47 This block specifies the address range of all global 48 configuration registers for the SEC 4 block. It 49 also receives interrupts from the Run Time Integrity Check 50 (RTIC) function within the SEC 4 block. 51 52 PROPERTIES 53 54 - compatible 55 Usage: required 56 Value type: <string> 57 Definition: Must include "fsl,sec-v4.0" 58 59 - fsl,sec-era 60 Usage: optional 61 Value type: <u32> 62 Definition: A standard property. Define the 'ERA' of the SEC 63 device. 64 65 - #address-cells 66 Usage: required 67 Value type: <u32> 68 Definition: A standard property. Defines the number of cells 69 for representing physical addresses in child nodes. 70 71 - #size-cells 72 Usage: required 73 Value type: <u32> 74 Definition: A standard property. Defines the number of cells 75 for representing the size of physical addresses in 76 child nodes. 77 78 - reg 79 Usage: required 80 Value type: <prop-encoded-array> 81 Definition: A standard property. Specifies the physical 82 address and length of the SEC4 configuration registers. 83 registers 84 85 - ranges 86 Usage: required 87 Value type: <prop-encoded-array> 88 Definition: A standard property. Specifies the physical address 89 range of the SEC 4.0 register space (-SNVS not included). A 90 triplet that includes the child address, parent address, & 91 length. 92 93 - interrupts 94 Usage: required 95 Value type: <prop_encoded-array> 96 Definition: Specifies the interrupts generated by this 97 device. The value of the interrupts property 98 consists of one interrupt specifier. The format 99 of the specifier is defined by the binding document 100 describing the node's interrupt parent. 101 102 - clocks 103 Usage: required if SEC 4.0 requires explicit enablement of clocks 104 Value type: <prop_encoded-array> 105 Definition: A list of phandle and clock specifier pairs describing 106 the clocks required for enabling and disabling SEC 4.0. 107 108 - clock-names 109 Usage: required if SEC 4.0 requires explicit enablement of clocks 110 Value type: <string> 111 Definition: A list of clock name strings in the same order as the 112 clocks property. 113 114 Note: All other standard properties (see the Devicetree Specification) 115 are allowed but are optional. 116 117 118 EXAMPLE 119 120 iMX6QDL/SX requires four clocks 121 122 crypto@300000 { 123 compatible = "fsl,sec-v4.0"; 124 fsl,sec-era = <2>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 reg = <0x300000 0x10000>; 128 ranges = <0 0x300000 0x10000>; 129 interrupt-parent = <&mpic>; 130 interrupts = <92 2>; 131 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 132 <&clks IMX6QDL_CLK_CAAM_ACLK>, 133 <&clks IMX6QDL_CLK_CAAM_IPG>, 134 <&clks IMX6QDL_CLK_EIM_SLOW>; 135 clock-names = "mem", "aclk", "ipg", "emi_slow"; 136 }; 137 138 139 iMX6UL does only require three clocks 140 141 crypto: crypto@2140000 { 142 compatible = "fsl,sec-v4.0"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 reg = <0x2140000 0x3c000>; 146 ranges = <0 0x2140000 0x3c000>; 147 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 148 149 clocks = <&clks IMX6UL_CLK_CAAM_MEM>, 150 <&clks IMX6UL_CLK_CAAM_ACLK>, 151 <&clks IMX6UL_CLK_CAAM_IPG>; 152 clock-names = "mem", "aclk", "ipg"; 153 }; 154 155 ===================================================================== 156 Job Ring (JR) Node 157 158 Child of the crypto node defines data processing interface to SEC 4 159 across the peripheral bus for purposes of processing 160 cryptographic descriptors. The specified address 161 range can be made visible to one (or more) cores. 162 The interrupt defined for this node is controlled within 163 the address range of this node. 164 165 - compatible 166 Usage: required 167 Value type: <string> 168 Definition: Must include "fsl,sec-v4.0-job-ring" 169 170 - reg 171 Usage: required 172 Value type: <prop-encoded-array> 173 Definition: Specifies a two JR parameters: an offset from 174 the parent physical address and the length the JR registers. 175 176 - fsl,liodn 177 Usage: optional-but-recommended 178 Value type: <prop-encoded-array> 179 Definition: 180 Specifies the LIODN to be used in conjunction with 181 the ppid-to-liodn table that specifies the PPID to LIODN mapping. 182 Needed if the PAMU is used. Value is a 12 bit value 183 where value is a LIODN ID for this JR. This property is 184 normally set by boot firmware. 185 186 - interrupts 187 Usage: required 188 Value type: <prop_encoded-array> 189 Definition: Specifies the interrupts generated by this 190 device. The value of the interrupts property 191 consists of one interrupt specifier. The format 192 of the specifier is defined by the binding document 193 describing the node's interrupt parent. 194 195 EXAMPLE 196 jr@1000 { 197 compatible = "fsl,sec-v4.0-job-ring"; 198 reg = <0x1000 0x1000>; 199 fsl,liodn = <0x081>; 200 interrupt-parent = <&mpic>; 201 interrupts = <88 2>; 202 }; 203 204 205 ===================================================================== 206 Run Time Integrity Check (RTIC) Node 207 208 Child node of the crypto node. Defines a register space that 209 contains up to 5 sets of addresses and their lengths (sizes) that 210 will be checked at run time. After an initial hash result is 211 calculated, these addresses are checked by HW to monitor any 212 change. If any memory is modified, a Security Violation is 213 triggered (see SNVS definition). 214 215 216 - compatible 217 Usage: required 218 Value type: <string> 219 Definition: Must include "fsl,sec-v4.0-rtic". 220 221 - #address-cells 222 Usage: required 223 Value type: <u32> 224 Definition: A standard property. Defines the number of cells 225 for representing physical addresses in child nodes. Must 226 have a value of 1. 227 228 - #size-cells 229 Usage: required 230 Value type: <u32> 231 Definition: A standard property. Defines the number of cells 232 for representing the size of physical addresses in 233 child nodes. Must have a value of 1. 234 235 - reg 236 Usage: required 237 Value type: <prop-encoded-array> 238 Definition: A standard property. Specifies a two parameters: 239 an offset from the parent physical address and the length 240 the SEC4 registers. 241 242 - ranges 243 Usage: required 244 Value type: <prop-encoded-array> 245 Definition: A standard property. Specifies the physical address 246 range of the SEC 4 register space (-SNVS not included). A 247 triplet that includes the child address, parent address, & 248 length. 249 250 EXAMPLE 251 rtic@6000 { 252 compatible = "fsl,sec-v4.0-rtic"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 reg = <0x6000 0x100>; 256 ranges = <0x0 0x6100 0xe00>; 257 }; 258 259 ===================================================================== 260 Run Time Integrity Check (RTIC) Memory Node 261 A child node that defines individual RTIC memory regions that are used to 262 perform run-time integrity check of memory areas that should not modified. 263 The node defines a register that contains the memory address & 264 length (combined) and a second register that contains the hash result 265 in big endian format. 266 267 - compatible 268 Usage: required 269 Value type: <string> 270 Definition: Must include "fsl,sec-v4.0-rtic-memory". 271 272 - reg 273 Usage: required 274 Value type: <prop-encoded-array> 275 Definition: A standard property. Specifies two parameters: 276 an offset from the parent physical address and the length: 277 278 1. The location of the RTIC memory address & length registers. 279 2. The location RTIC hash result. 280 281 - fsl,rtic-region 282 Usage: optional-but-recommended 283 Value type: <prop-encoded-array> 284 Definition: 285 Specifies the HW address (36 bit address) for this region 286 followed by the length of the HW partition to be checked; 287 the address is represented as a 64 bit quantity followed 288 by a 32 bit length. 289 290 - fsl,liodn 291 Usage: optional-but-recommended 292 Value type: <prop-encoded-array> 293 Definition: 294 Specifies the LIODN to be used in conjunction with 295 the ppid-to-liodn table that specifies the PPID to LIODN 296 mapping. Needed if the PAMU is used. Value is a 12 bit value 297 where value is a LIODN ID for this RTIC memory region. This 298 property is normally set by boot firmware. 299 300 EXAMPLE 301 rtic-a@0 { 302 compatible = "fsl,sec-v4.0-rtic-memory"; 303 reg = <0x00 0x20 0x100 0x80>; 304 fsl,liodn = <0x03c>; 305 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>; 306 }; 307 308 ===================================================================== 309 Secure Non-Volatile Storage (SNVS) Node 310 311 Node defines address range and the associated 312 interrupt for the SNVS function. This function 313 monitors security state information & reports 314 security violations. This also included rtc, 315 system power off and ON/OFF key. 316 317 - compatible 318 Usage: required 319 Value type: <string> 320 Definition: Must include "fsl,sec-v4.0-mon" and "syscon". 321 322 - reg 323 Usage: required 324 Value type: <prop-encoded-array> 325 Definition: A standard property. Specifies the physical 326 address and length of the SEC4 configuration 327 registers. 328 329 - #address-cells 330 Usage: required 331 Value type: <u32> 332 Definition: A standard property. Defines the number of cells 333 for representing physical addresses in child nodes. Must 334 have a value of 1. 335 336 - #size-cells 337 Usage: required 338 Value type: <u32> 339 Definition: A standard property. Defines the number of cells 340 for representing the size of physical addresses in 341 child nodes. Must have a value of 1. 342 343 - ranges 344 Usage: required 345 Value type: <prop-encoded-array> 346 Definition: A standard property. Specifies the physical address 347 range of the SNVS register space. A triplet that includes 348 the child address, parent address, & length. 349 350 - interrupts 351 Usage: optional 352 Value type: <prop_encoded-array> 353 Definition: Specifies the interrupts generated by this 354 device. The value of the interrupts property 355 consists of one interrupt specifier. The format 356 of the specifier is defined by the binding document 357 describing the node's interrupt parent. 358 359 EXAMPLE 360 sec_mon@314000 { 361 compatible = "fsl,sec-v4.0-mon", "syscon"; 362 reg = <0x314000 0x1000>; 363 ranges = <0 0x314000 0x1000>; 364 interrupt-parent = <&mpic>; 365 interrupts = <93 2>; 366 }; 367 368 ===================================================================== 369 Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node 370 371 A SNVS child node that defines SNVS LP RTC. 372 373 - compatible 374 Usage: required 375 Value type: <string> 376 Definition: Must include "fsl,sec-v4.0-mon-rtc-lp". 377 378 - interrupts 379 Usage: required 380 Value type: <prop_encoded-array> 381 Definition: Specifies the interrupts generated by this 382 device. The value of the interrupts property 383 consists of one interrupt specifier. The format 384 of the specifier is defined by the binding document 385 describing the node's interrupt parent. 386 387 - regmap 388 Usage: required 389 Value type: <phandle> 390 Definition: this is phandle to the register map node. 391 392 - offset 393 Usage: option 394 value type: <u32> 395 Definition: LP register offset. default it is 0x34. 396 397 - clocks 398 Usage: optional, required if SNVS LP RTC requires explicit 399 enablement of clocks 400 Value type: <prop_encoded-array> 401 Definition: a clock specifier describing the clock required for 402 enabling and disabling SNVS LP RTC. 403 404 - clock-names 405 Usage: optional, required if SNVS LP RTC requires explicit 406 enablement of clocks 407 Value type: <string> 408 Definition: clock name string should be "snvs-rtc". 409 410 EXAMPLE 411 sec_mon_rtc_lp@1 { 412 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 413 interrupts = <93 2>; 414 regmap = <&snvs>; 415 offset = <0x34>; 416 clocks = <&clks IMX7D_SNVS_CLK>; 417 clock-names = "snvs-rtc"; 418 }; 419 420 ===================================================================== 421 System ON/OFF key driver 422 423 The snvs-pwrkey is designed to enable POWER key function which controlled 424 by SNVS ONOFF, the driver can report the status of POWER key and wakeup 425 system if pressed after system suspend. 426 427 - compatible: 428 Usage: required 429 Value type: <string> 430 Definition: Mush include "fsl,sec-v4.0-pwrkey". 431 432 - interrupts: 433 Usage: required 434 Value type: <prop_encoded-array> 435 Definition: The SNVS ON/OFF interrupt number to the CPU(s). 436 437 - linux,keycode: 438 Usage: option 439 Value type: <int> 440 Definition: Keycode to emit, KEY_POWER by default. 441 442 - wakeup-source: 443 Usage: option 444 Value type: <boo> 445 Definition: Button can wake-up the system. 446 447 - regmap: 448 Usage: required: 449 Value type: <phandle> 450 Definition: this is phandle to the register map node. 451 452 EXAMPLE: 453 snvs-pwrkey@020cc000 { 454 compatible = "fsl,sec-v4.0-pwrkey"; 455 regmap = <&snvs>; 456 interrupts = <0 4 0x4> 457 linux,keycode = <116>; /* KEY_POWER */ 458 wakeup-source; 459 }; 460 461 ===================================================================== 462 FULL EXAMPLE 463 464 crypto: crypto@300000 { 465 compatible = "fsl,sec-v4.0"; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 reg = <0x300000 0x10000>; 469 ranges = <0 0x300000 0x10000>; 470 interrupt-parent = <&mpic>; 471 interrupts = <92 2>; 472 473 sec_jr0: jr@1000 { 474 compatible = "fsl,sec-v4.0-job-ring"; 475 reg = <0x1000 0x1000>; 476 interrupt-parent = <&mpic>; 477 interrupts = <88 2>; 478 }; 479 480 sec_jr1: jr@2000 { 481 compatible = "fsl,sec-v4.0-job-ring"; 482 reg = <0x2000 0x1000>; 483 interrupt-parent = <&mpic>; 484 interrupts = <89 2>; 485 }; 486 487 sec_jr2: jr@3000 { 488 compatible = "fsl,sec-v4.0-job-ring"; 489 reg = <0x3000 0x1000>; 490 interrupt-parent = <&mpic>; 491 interrupts = <90 2>; 492 }; 493 494 sec_jr3: jr@4000 { 495 compatible = "fsl,sec-v4.0-job-ring"; 496 reg = <0x4000 0x1000>; 497 interrupt-parent = <&mpic>; 498 interrupts = <91 2>; 499 }; 500 501 rtic@6000 { 502 compatible = "fsl,sec-v4.0-rtic"; 503 #address-cells = <1>; 504 #size-cells = <1>; 505 reg = <0x6000 0x100>; 506 ranges = <0x0 0x6100 0xe00>; 507 508 rtic_a: rtic-a@0 { 509 compatible = "fsl,sec-v4.0-rtic-memory"; 510 reg = <0x00 0x20 0x100 0x80>; 511 }; 512 513 rtic_b: rtic-b@20 { 514 compatible = "fsl,sec-v4.0-rtic-memory"; 515 reg = <0x20 0x20 0x200 0x80>; 516 }; 517 518 rtic_c: rtic-c@40 { 519 compatible = "fsl,sec-v4.0-rtic-memory"; 520 reg = <0x40 0x20 0x300 0x80>; 521 }; 522 523 rtic_d: rtic-d@60 { 524 compatible = "fsl,sec-v4.0-rtic-memory"; 525 reg = <0x60 0x20 0x500 0x80>; 526 }; 527 }; 528 }; 529 530 sec_mon: sec_mon@314000 { 531 compatible = "fsl,sec-v4.0-mon"; 532 reg = <0x314000 0x1000>; 533 ranges = <0 0x314000 0x1000>; 534 535 sec_mon_rtc_lp@34 { 536 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 537 regmap = <&sec_mon>; 538 offset = <0x34>; 539 interrupts = <93 2>; 540 clocks = <&clks IMX7D_SNVS_CLK>; 541 clock-names = "snvs-rtc"; 542 }; 543 544 snvs-pwrkey@020cc000 { 545 compatible = "fsl,sec-v4.0-pwrkey"; 546 regmap = <&sec_mon>; 547 interrupts = <0 4 0x4>; 548 linux,keycode = <116>; /* KEY_POWER */ 549 wakeup-source; 550 }; 551 }; 552 553 =====================================================================
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