The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/crypto/hisilicon,hip07-sec.txt

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    1 * Hisilicon hip07 Security Accelerator (SEC)
    2 
    3 Required properties:
    4 - compatible: Must contain one of
    5   - "hisilicon,hip06-sec"
    6   - "hisilicon,hip07-sec"
    7 - reg: Memory addresses and lengths of the memory regions through which
    8   this device is controlled.
    9   Region 0 has registers to control the backend processing engines.
   10   Region 1 has registers for functionality common to all queues.
   11   Regions 2-18 have registers for the 16 individual queues which are isolated
   12   both in hardware and within the driver.
   13 - interrupts: Interrupt specifiers.
   14   Refer to interrupt-controller/interrupts.txt for generic interrupt client node
   15   bindings.
   16   Interrupt 0 is for the SEC unit error queue.
   17   Interrupt 2N + 1 is the completion interrupt for queue N.
   18   Interrupt 2N + 2 is the error interrupt for queue N.
   19 - dma-coherent:  The driver assumes coherent dma is possible.
   20 
   21 Optional properties:
   22 - iommus: The SEC units are behind smmu-v3 iommus.
   23   Refer to iommu/arm,smmu-v3.txt for more information.
   24 
   25 Example:
   26 
   27 p1_sec_a: crypto@400d2000000 {
   28         compatible = "hisilicon,hip07-sec";
   29         reg = <0x400 0xd0000000 0x0 0x10000
   30                0x400 0xd2000000 0x0 0x10000
   31                0x400 0xd2010000 0x0 0x10000
   32                0x400 0xd2020000 0x0 0x10000
   33                0x400 0xd2030000 0x0 0x10000
   34                0x400 0xd2040000 0x0 0x10000
   35                0x400 0xd2050000 0x0 0x10000
   36                0x400 0xd2060000 0x0 0x10000
   37                0x400 0xd2070000 0x0 0x10000
   38                0x400 0xd2080000 0x0 0x10000
   39                0x400 0xd2090000 0x0 0x10000
   40                0x400 0xd20a0000 0x0 0x10000
   41                0x400 0xd20b0000 0x0 0x10000
   42                0x400 0xd20c0000 0x0 0x10000
   43                0x400 0xd20d0000 0x0 0x10000
   44                0x400 0xd20e0000 0x0 0x10000
   45                0x400 0xd20f0000 0x0 0x10000
   46                0x400 0xd2100000 0x0 0x10000>;
   47         interrupt-parent = <&p1_mbigen_sec_a>;
   48         iommus = <&p1_smmu_alg_a 0x600>;
   49         dma-coherent;
   50         interrupts = <576 4>,
   51                      <577 1>, <578 4>,
   52                      <579 1>, <580 4>,
   53                      <581 1>, <582 4>,
   54                      <583 1>, <584 4>,
   55                      <585 1>, <586 4>,
   56                      <587 1>, <588 4>,
   57                      <589 1>, <590 4>,
   58                      <591 1>, <592 4>,
   59                      <593 1>, <594 4>,
   60                      <595 1>, <596 4>,
   61                      <597 1>, <598 4>,
   62                      <599 1>, <600 4>,
   63                      <601 1>, <602 4>,
   64                      <603 1>, <604 4>,
   65                      <605 1>, <606 4>,
   66                      <607 1>, <608 4>;
   67 };

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