Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/devfreq/rk3399_dmc.txt
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1 * Rockchip rk3399 DMC (Dynamic Memory Controller) device 2 3 Required properties: 4 - compatible: Must be "rockchip,rk3399-dmc". 5 - devfreq-events: Node to get DDR loading, Refer to 6 Documentation/devicetree/bindings/devfreq/event/ 7 rockchip-dfi.txt 8 - clocks: Phandles for clock specified in "clock-names" property 9 - clock-names : The name of clock used by the DFI, must be 10 "pclk_ddr_mon"; 11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml 12 for details. 13 - center-supply: DMC supply node. 14 - status: Marks the node enabled/disabled. 15 - rockchip,pmu: Phandle to the syscon managing the "PMU general register 16 files". 17 18 Optional properties: 19 - interrupts: The CPU interrupt number. The interrupt specifier 20 format depends on the interrupt controller. 21 It should be a DCF interrupt. When DDR DVFS finishes 22 a DCF interrupt is triggered. 23 - rockchip,pmu: Phandle to the syscon managing the "PMU general register 24 files". 25 26 Following properties relate to DDR timing: 27 28 - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h, 29 it selects the DDR3 cl-trp-trcd type. It must be 30 set according to "Speed Bin" in DDR3 datasheet, 31 DO NOT use a smaller "Speed Bin" than specified 32 for the DDR3 being used. 33 34 - rockchip,pd_idle : Configure the PD_IDLE value. Defines the 35 power-down idle period in which memories are 36 placed into power-down mode if bus is idle 37 for PD_IDLE DFI clock cycles. 38 39 - rockchip,sr_idle : Configure the SR_IDLE value. Defines the 40 self-refresh idle period in which memories are 41 placed into self-refresh mode if bus is idle 42 for SR_IDLE * 1024 DFI clock cycles (DFI 43 clocks freq is half of DRAM clock), default 44 value is "0". 45 46 - rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller 47 clock gating idle period. Memories are placed 48 into self-refresh mode and memory controller 49 clock arg gating started if bus is idle for 50 sr_mc_gate_idle*1024 DFI clock cycles. 51 52 - rockchip,srpd_lite_idle : Defines the self-refresh power down idle 53 period in which memories are placed into 54 self-refresh power down mode if bus is idle 55 for srpd_lite_idle * 1024 DFI clock cycles. 56 This parameter is for LPDDR4 only. 57 58 - rockchip,standby_idle : Defines the standby idle period in which 59 memories are placed into self-refresh mode. 60 The controller, pi, PHY and DRAM clock will 61 be gated if bus is idle for standby_idle * DFI 62 clock cycles. 63 64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz. 65 When DDR frequency is less than DRAM_DLL_DISB_FREQ, 66 DDR3 DLL will be bypassed. Note: if DLL was bypassed, 67 the odt will also stop working. 68 69 - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in 70 MHz (Mega Hz). When DDR frequency is less than 71 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed. 72 Note: PHY DLL and PHY ODT are independent. 73 74 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines 75 the ODT disable frequency in MHz (Mega Hz). 76 when the DDR frequency is less then ddr3_odt_dis_freq, 77 the ODT on the DRAM side and controller side are 78 both disabled. 79 80 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines 81 the DRAM side driver strength in ohms. Default 82 value is 40. 83 84 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines 85 the DRAM side ODT strength in ohms. Default value 86 is 120. 87 88 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines 89 the phy side CA line (incluing command line, 90 address line and clock line) driver strength. 91 Default value is 40. 92 93 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines 94 the PHY side DQ line (including DQS/DQ/DM line) 95 driver strength. Default value is 40. 96 97 - rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines 98 the PHY side ODT strength. Default value is 240. 99 100 - rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines 101 then ODT disable frequency in MHz (Mega Hz). 102 When DDR frequency is less then ddr3_odt_dis_freq, 103 the ODT on the DRAM side and controller side are 104 both disabled. 105 106 - rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines 107 the DRAM side driver strength in ohms. Default 108 value is 34. 109 110 - rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines 111 the DRAM side ODT strength in ohms. Default value 112 is 240. 113 114 - rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines 115 the PHY side CA line (including command line, 116 address line and clock line) driver strength. 117 Default value is 40. 118 119 - rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines 120 the PHY side DQ line (including DQS/DQ/DM line) 121 driver strength. Default value is 40. 122 123 - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define 124 the phy side odt strength, default value is 240. 125 126 - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter 127 defines the ODT disable frequency in 128 MHz (Mega Hz). When the DDR frequency is less then 129 ddr3_odt_dis_freq, the ODT on the DRAM side and 130 controller side are both disabled. 131 132 - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines 133 the DRAM side driver strength in ohms. Default 134 value is 60. 135 136 - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines 137 the DRAM side ODT on DQS/DQ line strength in ohms. 138 Default value is 40. 139 140 - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines 141 the DRAM side ODT on CA line strength in ohms. 142 Default value is 40. 143 144 - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines 145 the PHY side CA line (including command address 146 line) driver strength. Default value is 40. 147 148 - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines 149 the PHY side clock line and CS line driver 150 strength. Default value is 80. 151 152 - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines 153 the PHY side DQ line (including DQS/DQ/DM line) 154 driver strength. Default value is 80. 155 156 - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines 157 the PHY side ODT strength. Default value is 60. 158 159 Example: 160 dmc_opp_table: dmc_opp_table { 161 compatible = "operating-points-v2"; 162 163 opp00 { 164 opp-hz = /bits/ 64 <300000000>; 165 opp-microvolt = <900000>; 166 }; 167 opp01 { 168 opp-hz = /bits/ 64 <666000000>; 169 opp-microvolt = <900000>; 170 }; 171 }; 172 173 dmc: dmc { 174 compatible = "rockchip,rk3399-dmc"; 175 devfreq-events = <&dfi>; 176 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&cru SCLK_DDRC>; 178 clock-names = "dmc_clk"; 179 operating-points-v2 = <&dmc_opp_table>; 180 center-supply = <&ppvar_centerlogic>; 181 upthreshold = <15>; 182 downdifferential = <10>; 183 rockchip,ddr3_speed_bin = <21>; 184 rockchip,pd_idle = <0x40>; 185 rockchip,sr_idle = <0x2>; 186 rockchip,sr_mc_gate_idle = <0x3>; 187 rockchip,srpd_lite_idle = <0x4>; 188 rockchip,standby_idle = <0x2000>; 189 rockchip,dram_dll_dis_freq = <300>; 190 rockchip,phy_dll_dis_freq = <125>; 191 rockchip,auto_pd_dis_freq = <666>; 192 rockchip,ddr3_odt_dis_freq = <333>; 193 rockchip,ddr3_drv = <40>; 194 rockchip,ddr3_odt = <120>; 195 rockchip,phy_ddr3_ca_drv = <40>; 196 rockchip,phy_ddr3_dq_drv = <40>; 197 rockchip,phy_ddr3_odt = <240>; 198 rockchip,lpddr3_odt_dis_freq = <333>; 199 rockchip,lpddr3_drv = <34>; 200 rockchip,lpddr3_odt = <240>; 201 rockchip,phy_lpddr3_ca_drv = <40>; 202 rockchip,phy_lpddr3_dq_drv = <40>; 203 rockchip,phy_lpddr3_odt = <240>; 204 rockchip,lpddr4_odt_dis_freq = <333>; 205 rockchip,lpddr4_drv = <60>; 206 rockchip,lpddr4_dq_odt = <40>; 207 rockchip,lpddr4_ca_odt = <40>; 208 rockchip,phy_lpddr4_ca_drv = <40>; 209 rockchip,phy_lpddr4_ck_cs_drv = <80>; 210 rockchip,phy_lpddr4_dq_drv = <80>; 211 rockchip,phy_lpddr4_odt = <60>; 212 };
Cache object: 0f3f714e3c910dce8a16a37e4606cd5b
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