allwinner,sun8i-a83t-dw-hdmi.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
    8 
    9 description: |
   10   The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
   11   IP with Allwinner\'s own PHY IP. It supports audio and video outputs
   12   and CEC.
   13 
   14   These DT bindings follow the Synopsys DWC HDMI TX bindings defined
   15   in bridge/synopsys,dw-hdmi.yaml with the following device-specific
   16   properties.
   17 
   18 maintainers:
   19   - Chen-Yu Tsai <wens@csie.org>
   20   - Maxime Ripard <mripard@kernel.org>
   21 
   22 properties:
   23   "#phy-cells":
   24     const: 0
   25 
   26   compatible:
   27     oneOf:
   28       - const: allwinner,sun8i-a83t-dw-hdmi
   29       - const: allwinner,sun50i-h6-dw-hdmi
   30 
   31       - items:
   32           - enum:
   33               - allwinner,sun8i-h3-dw-hdmi
   34               - allwinner,sun8i-r40-dw-hdmi
   35               - allwinner,sun50i-a64-dw-hdmi
   36           - const: allwinner,sun8i-a83t-dw-hdmi
   37 
   38   reg:
   39     maxItems: 1
   40 
   41   reg-io-width:
   42     const: 1
   43 
   44   interrupts:
   45     maxItems: 1
   46 
   47   clocks:
   48     minItems: 3
   49     items:
   50       - description: Bus Clock
   51       - description: Register Clock
   52       - description: TMDS Clock
   53       - description: HDMI CEC Clock
   54       - description: HDCP Clock
   55       - description: HDCP Bus Clock
   56 
   57   clock-names:
   58     minItems: 3
   59     items:
   60       - const: iahb
   61       - const: isfr
   62       - const: tmds
   63       - const: cec
   64       - const: hdcp
   65       - const: hdcp-bus
   66 
   67   resets:
   68     minItems: 1
   69     items:
   70       - description: HDMI Controller Reset
   71       - description: HDCP Reset
   72 
   73   reset-names:
   74     minItems: 1
   75     items:
   76       - const: ctrl
   77       - const: hdcp
   78 
   79   phys:
   80     maxItems: 1
   81     description:
   82       Phandle to the DWC HDMI PHY.
   83 
   84   phy-names:
   85     const: phy
   86 
   87   hvcc-supply:
   88     description:
   89       The VCC power supply of the controller
   90 
   91   ports:
   92     $ref: /schemas/graph.yaml#/properties/ports
   93 
   94     properties:
   95       port@0:
   96         $ref: /schemas/graph.yaml#/properties/port
   97         description: |
   98           Input endpoints of the controller. Usually the associated
   99           TCON.
  100 
  101       port@1:
  102         $ref: /schemas/graph.yaml#/properties/port
  103         description: |
  104           Output endpoints of the controller. Usually an HDMI
  105           connector.
  106 
  107     required:
  108       - port@0
  109       - port@1
  110 
  111 required:
  112   - compatible
  113   - reg
  114   - reg-io-width
  115   - interrupts
  116   - clocks
  117   - clock-names
  118   - resets
  119   - reset-names
  120   - phys
  121   - phy-names
  122   - ports
  123 
  124 if:
  125   properties:
  126     compatible:
  127       contains:
  128         enum:
  129           - allwinner,sun50i-h6-dw-hdmi
  130 
  131 then:
  132   properties:
  133     clocks:
  134       minItems: 6
  135 
  136     clock-names:
  137       minItems: 6
  138 
  139     resets:
  140       minItems: 2
  141 
  142     reset-names:
  143       minItems: 2
  144 
  145 
  146 additionalProperties: false
  147 
  148 examples:
  149   - |
  150     #include <dt-bindings/interrupt-controller/arm-gic.h>
  151 
  152     /*
  153      * This comes from the clock/sun8i-a83t-ccu.h and
  154      * reset/sun8i-a83t-ccu.h headers, but we can't include them since
  155      * it would trigger a bunch of warnings for redefinitions of
  156      * symbols with the other example.
  157      */
  158     #define CLK_BUS_HDMI        39
  159     #define CLK_HDMI            93
  160     #define CLK_HDMI_SLOW       94
  161     #define RST_BUS_HDMI1       26
  162 
  163     hdmi@1ee0000 {
  164         compatible = "allwinner,sun8i-a83t-dw-hdmi";
  165         reg = <0x01ee0000 0x10000>;
  166         reg-io-width = <1>;
  167         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  168         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
  169                  <&ccu CLK_HDMI>;
  170         clock-names = "iahb", "isfr", "tmds";
  171         resets = <&ccu RST_BUS_HDMI1>;
  172         reset-names = "ctrl";
  173         phys = <&hdmi_phy>;
  174         phy-names = "phy";
  175         pinctrl-names = "default";
  176         pinctrl-0 = <&hdmi_pins>;
  177 
  178         ports {
  179             #address-cells = <1>;
  180             #size-cells = <0>;
  181 
  182             port@0 {
  183                 reg = <0>;
  184 
  185                 endpoint {
  186                     remote-endpoint = <&tcon1_out_hdmi>;
  187                 };
  188             };
  189 
  190             port@1 {
  191                 reg = <1>;
  192             };
  193         };
  194     };
  195 
  196     /* Cleanup after ourselves */
  197     #undef CLK_BUS_HDMI
  198     #undef CLK_HDMI
  199     #undef CLK_HDMI_SLOW
  200 
  201   - |
  202     #include <dt-bindings/interrupt-controller/arm-gic.h>
  203 
  204     /*
  205      * This comes from the clock/sun50i-h6-ccu.h and
  206      * reset/sun50i-h6-ccu.h headers, but we can't include them since
  207      * it would trigger a bunch of warnings for redefinitions of
  208      * symbols with the other example.
  209      */
  210     #define CLK_BUS_HDMI        126
  211     #define CLK_BUS_HDCP        137
  212     #define CLK_HDMI            123
  213     #define CLK_HDMI_SLOW       124
  214     #define CLK_HDMI_CEC        125
  215     #define CLK_HDCP            136
  216     #define RST_BUS_HDMI_SUB    57
  217     #define RST_BUS_HDCP        62
  218 
  219     hdmi@6000000 {
  220         compatible = "allwinner,sun50i-h6-dw-hdmi";
  221         reg = <0x06000000 0x10000>;
  222         reg-io-width = <1>;
  223         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  224         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
  225                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
  226                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
  227         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
  228                       "hdcp-bus";
  229         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
  230         reset-names = "ctrl", "hdcp";
  231         phys = <&hdmi_phy>;
  232         phy-names = "phy";
  233         pinctrl-names = "default";
  234         pinctrl-0 = <&hdmi_pins>;
  235 
  236         ports {
  237             #address-cells = <1>;
  238             #size-cells = <0>;
  239 
  240             port@0 {
  241                 reg = <0>;
  242 
  243                 endpoint {
  244                     remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
  245                 };
  246             };
  247 
  248             port@1 {
  249                 reg = <1>;
  250             };
  251         };
  252     };
  253 
  254 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml

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sys/contrib/device-tree/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml