The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/bridge/renesas,lvds.txt

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    1 Renesas R-Car LVDS Encoder
    2 ==========================
    3 
    4 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
    5 Gen2, R-Car Gen3 and RZ/G SoCs.
    6 
    7 Required properties:
    8 
    9 - compatible : Shall contain one of
   10   - "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
   11   - "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
   12   - "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
   13   - "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders
   14   - "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
   15   - "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
   16   - "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
   17   - "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
   18   - "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
   19   - "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
   20   - "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders
   21   - "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
   22   - "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders
   23   - "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders
   24   - "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
   25 
   26 - reg: Base address and length for the memory-mapped registers
   27 - clocks: A list of phandles + clock-specifier pairs, one for each entry in
   28   the clock-names property.
   29 - clock-names: Name of the clocks. This property is model-dependent.
   30   - The functional clock, which mandatory for all models, shall be listed
   31     first, and shall be named "fck".
   32   - On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or
   33     DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
   34     named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
   35     numerical index.
   36   - When the clocks property only contains the functional clock, the
   37     clock-names property may be omitted.
   38 - resets: A phandle + reset specifier for the module reset
   39 
   40 Required nodes:
   41 
   42 The LVDS encoder has two video ports. Their connections are modelled using the
   43 OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
   44 
   45 - Video port 0 corresponds to the parallel RGB input
   46 - Video port 1 corresponds to the LVDS output
   47 
   48 Each port shall have a single endpoint.
   49 
   50 Optional properties:
   51 
   52 - renesas,companion : phandle to the companion LVDS encoder. This property is
   53   mandatory for the first LVDS encoder on D3 and E3 SoCs, and shall point to
   54   the second encoder to be used as a companion in dual-link mode. It shall not
   55   be set for any other LVDS encoder.
   56 
   57 
   58 Example:
   59 
   60         lvds0: lvds@feb90000 {
   61                 compatible = "renesas,r8a77990-lvds";
   62                 reg = <0 0xfeb90000 0 0x20>;
   63                 clocks = <&cpg CPG_MOD 727>;
   64                 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
   65                 resets = <&cpg 727>;
   66 
   67                 renesas,companion = <&lvds1>;
   68 
   69                 ports {
   70                         #address-cells = <1>;
   71                         #size-cells = <0>;
   72 
   73                         port@0 {
   74                                 reg = <0>;
   75                                 lvds0_in: endpoint {
   76                                         remote-endpoint = <&du_out_lvds0>;
   77                                 };
   78                         };
   79                         port@1 {
   80                                 reg = <1>;
   81                                 lvds0_out: endpoint {
   82                                 };
   83                         };
   84                 };
   85         };

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