FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.txt

     Mediatek DSI Device
     ===================
     
     The Mediatek DSI function block is a sink of the display subsystem and can
     drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
     channel output.
     
     Required properties:
     - compatible: "mediatek,<chip>-dsi"
    - the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
    - reg: Physical base address and length of the controller's registers
    - interrupts: The interrupt signal from the function block.
    - clocks: device clocks
      See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
    - clock-names: must contain "engine", "digital", and "hs"
    - phys: phandle link to the MIPI D-PHY controller.
    - phy-names: must contain "dphy"
    - port: Output port node with endpoint definitions as described in
      Documentation/devicetree/bindings/graph.txt. This port should be connected
      to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
    
    Optional properties:
    - resets: list of phandle + reset specifier pair, as described in [1].
    
    [1] Documentation/devicetree/bindings/reset/reset.txt
    
    MIPI TX Configuration Module
    ============================
    
    See phy/mediatek,dsi-phy.yaml
    
    Example:
    
    mipi_tx0: mipi-dphy@10215000 {
            compatible = "mediatek,mt8173-mipi-tx";
            reg = <0 0x10215000 0 0x1000>;
            clocks = <&clk26m>;
            clock-output-names = "mipi_tx0_pll";
            #clock-cells = <0>;
            #phy-cells = <0>;
            drive-strength-microamp = <4600>;
            nvmem-cells= <&mipi_tx_calibration>;
            nvmem-cell-names = "calibration-data";
    };
    
    dsi0: dsi@1401b000 {
            compatible = "mediatek,mt8173-dsi";
            reg = <0 0x1401b000 0 0x1000>;
            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
            clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
                     <&mipi_tx0>;
            clock-names = "engine", "digital", "hs";
            resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
            phys = <&mipi_tx0>;
            phy-names = "dphy";
    
            port {
                    dsi0_out: endpoint {
                            remote-endpoint = <&panel_in>;
                    };
            };
    };

Cache object: 992698b3f7b88c84240eb041e1293ecc