1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Mediatek mutex
8
9 maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12
13 description: |
14 Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15 Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16 data path or MDP data path.
17 In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
18 the shadow register.
19 MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20 For a description of the MMSYS_CONFIG binding, see
21 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
22 for details.
23
24 properties:
25 compatible:
26 enum:
27 - mediatek,mt2701-disp-mutex
28 - mediatek,mt2712-disp-mutex
29 - mediatek,mt8167-disp-mutex
30 - mediatek,mt8173-disp-mutex
31 - mediatek,mt8183-disp-mutex
32 - mediatek,mt8186-disp-mutex
33 - mediatek,mt8192-disp-mutex
34 - mediatek,mt8195-disp-mutex
35
36 reg:
37 maxItems: 1
38
39 interrupts:
40 maxItems: 1
41
42 power-domains:
43 description: A phandle and PM domain specifier as defined by bindings of
44 the power controller specified by phandle. See
45 Documentation/devicetree/bindings/power/power-domain.yaml for details.
46
47 clocks:
48 items:
49 - description: MUTEX Clock
50
51 mediatek,gce-events:
52 description:
53 The event id which is mapping to the specific hardware event signal
54 to gce. The event id is defined in the gce header
55 include/dt-bindings/gce/<chip>-gce.h of each chips.
56 $ref: /schemas/types.yaml#/definitions/uint32-array
57
58 required:
59 - compatible
60 - reg
61 - interrupts
62 - power-domains
63 - clocks
64
65 additionalProperties: false
66
67 examples:
68 - |
69 #include <dt-bindings/interrupt-controller/arm-gic.h>
70 #include <dt-bindings/clock/mt8173-clk.h>
71 #include <dt-bindings/power/mt8173-power.h>
72 #include <dt-bindings/gce/mt8173-gce.h>
73
74 soc {
75 #address-cells = <2>;
76 #size-cells = <2>;
77
78 mutex: mutex@14020000 {
79 compatible = "mediatek,mt8173-disp-mutex";
80 reg = <0 0x14020000 0 0x1000>;
81 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
82 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
83 clocks = <&mmsys CLK_MM_MUTEX_32K>;
84 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
85 <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
86 };
87 };
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