mediatek,ovl.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Mediatek display overlay
    8 
    9 maintainers:
   10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
   11   - Philipp Zabel <p.zabel@pengutronix.de>
   12 
   13 description: |
   14   Mediatek display overlay, namely OVL, can do alpha blending from
   15   the memory.
   16   OVL device node must be siblings to the central MMSYS_CONFIG node.
   17   For a description of the MMSYS_CONFIG binding, see
   18   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
   19   for details.
   20 
   21 properties:
   22   compatible:
   23     oneOf:
   24       - items:
   25           - const: mediatek,mt2701-disp-ovl
   26       - items:
   27           - const: mediatek,mt8173-disp-ovl
   28       - items:
   29           - const: mediatek,mt8183-disp-ovl
   30       - items:
   31           - const: mediatek,mt8192-disp-ovl
   32       - items:
   33           - enum:
   34               - mediatek,mt7623-disp-ovl
   35               - mediatek,mt2712-disp-ovl
   36           - const: mediatek,mt2701-disp-ovl
   37       - items:
   38           - enum:
   39               - mediatek,mt8195-disp-ovl
   40           - const: mediatek,mt8183-disp-ovl
   41       - items:
   42           - enum:
   43               - mediatek,mt8186-disp-ovl
   44           - const: mediatek,mt8192-disp-ovl
   45 
   46   reg:
   47     maxItems: 1
   48 
   49   interrupts:
   50     maxItems: 1
   51 
   52   power-domains:
   53     description: A phandle and PM domain specifier as defined by bindings of
   54       the power controller specified by phandle. See
   55       Documentation/devicetree/bindings/power/power-domain.yaml for details.
   56 
   57   clocks:
   58     items:
   59       - description: OVL Clock
   60 
   61   iommus:
   62     description:
   63       This property should point to the respective IOMMU block with master port as argument,
   64       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
   65 
   66   mediatek,gce-client-reg:
   67     description: The register of client driver can be configured by gce with
   68       4 arguments defined in this property, such as phandle of gce, subsys id,
   69       register offset and size. Each GCE subsys id is mapping to a client
   70       defined in the header include/dt-bindings/gce/<chip>-gce.h.
   71     $ref: /schemas/types.yaml#/definitions/phandle-array
   72     maxItems: 1
   73 
   74 required:
   75   - compatible
   76   - reg
   77   - interrupts
   78   - power-domains
   79   - clocks
   80   - iommus
   81 
   82 additionalProperties: false
   83 
   84 examples:
   85   - |
   86     #include <dt-bindings/interrupt-controller/arm-gic.h>
   87     #include <dt-bindings/clock/mt8173-clk.h>
   88     #include <dt-bindings/power/mt8173-power.h>
   89     #include <dt-bindings/gce/mt8173-gce.h>
   90     #include <dt-bindings/memory/mt8173-larb-port.h>
   91 
   92     soc {
   93         #address-cells = <2>;
   94         #size-cells = <2>;
   95 
   96         ovl0: ovl@1400c000 {
   97             compatible = "mediatek,mt8173-disp-ovl";
   98             reg = <0 0x1400c000 0 0x1000>;
   99             interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
  100             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  101             clocks = <&mmsys CLK_MM_DISP_OVL0>;
  102             iommus = <&iommu M4U_PORT_DISP_OVL0>;
  103             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
  104         };
  105     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/display/mediatek/mediatek,ovl.yaml

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sys/contrib/device-tree/Bindings/display/mediatek/mediatek,ovl.yaml