dpu-qcm2290.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Display DPU dt properties for QCM2290 target
    8 
    9 maintainers:
   10   - Loic Poulain <loic.poulain@linaro.org>
   11 
   12 description: |
   13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
   14   sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
   15   and DPU are mentioned for QCM2290 target.
   16 
   17 properties:
   18   compatible:
   19     items:
   20       - const: qcom,qcm2290-mdss
   21 
   22   reg:
   23     maxItems: 1
   24 
   25   reg-names:
   26     const: mdss
   27 
   28   power-domains:
   29     maxItems: 1
   30 
   31   clocks:
   32     items:
   33       - description: Display AHB clock from gcc
   34       - description: Display AXI clock
   35       - description: Display core clock
   36 
   37   clock-names:
   38     items:
   39       - const: iface
   40       - const: bus
   41       - const: core
   42 
   43   interrupts:
   44     maxItems: 1
   45 
   46   interrupt-controller: true
   47 
   48   "#address-cells": true
   49 
   50   "#size-cells": true
   51 
   52   "#interrupt-cells":
   53     const: 1
   54 
   55   iommus:
   56     items:
   57       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
   58       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
   59 
   60   ranges: true
   61 
   62   interconnects:
   63     items:
   64       - description: Interconnect path specifying the port ids for data bus
   65 
   66   interconnect-names:
   67     const: mdp0-mem
   68 
   69   resets:
   70     items:
   71       - description: MDSS_CORE reset
   72 
   73 patternProperties:
   74   "^display-controller@[0-9a-f]+$":
   75     type: object
   76     description: Node containing the properties of DPU.
   77 
   78     properties:
   79       compatible:
   80         items:
   81           - const: qcom,qcm2290-dpu
   82 
   83       reg:
   84         items:
   85           - description: Address offset and size for mdp register set
   86           - description: Address offset and size for vbif register set
   87 
   88       reg-names:
   89         items:
   90           - const: mdp
   91           - const: vbif
   92 
   93       clocks:
   94         items:
   95           - description: Display AXI clock from gcc
   96           - description: Display AHB clock from dispcc
   97           - description: Display core clock from dispcc
   98           - description: Display lut clock from dispcc
   99           - description: Display vsync clock from dispcc
  100 
  101       clock-names:
  102         items:
  103           - const: bus
  104           - const: iface
  105           - const: core
  106           - const: lut
  107           - const: vsync
  108 
  109       interrupts:
  110         maxItems: 1
  111 
  112       power-domains:
  113         maxItems: 1
  114 
  115       operating-points-v2: true
  116 
  117       ports:
  118         $ref: /schemas/graph.yaml#/properties/ports
  119         description: |
  120           Contains the list of output ports from DPU device. These ports
  121           connect to interfaces that are external to the DPU hardware,
  122           such as DSI. Each output port contains an endpoint that
  123           describes how it is connected to an external interface.
  124 
  125         properties:
  126           port@0:
  127             $ref: /schemas/graph.yaml#/properties/port
  128             description: DPU_INTF1 (DSI1)
  129 
  130         required:
  131           - port@0
  132 
  133     required:
  134       - compatible
  135       - reg
  136       - reg-names
  137       - clocks
  138       - interrupts
  139       - power-domains
  140       - operating-points-v2
  141       - ports
  142 
  143 required:
  144   - compatible
  145   - reg
  146   - reg-names
  147   - power-domains
  148   - clocks
  149   - interrupts
  150   - interrupt-controller
  151   - iommus
  152   - ranges
  153 
  154 additionalProperties: false
  155 
  156 examples:
  157   - |
  158     #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
  159     #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
  160     #include <dt-bindings/interrupt-controller/arm-gic.h>
  161     #include <dt-bindings/interconnect/qcom,qcm2290.h>
  162     #include <dt-bindings/power/qcom-rpmpd.h>
  163 
  164     mdss: mdss@5e00000 {
  165         #address-cells = <1>;
  166         #size-cells = <1>;
  167         compatible = "qcom,qcm2290-mdss";
  168         reg = <0x05e00000 0x1000>;
  169         reg-names = "mdss";
  170         power-domains = <&dispcc MDSS_GDSC>;
  171         clocks = <&gcc GCC_DISP_AHB_CLK>,
  172                  <&gcc GCC_DISP_HF_AXI_CLK>,
  173                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  174         clock-names = "iface", "bus", "core";
  175 
  176         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  177         interrupt-controller;
  178         #interrupt-cells = <1>;
  179 
  180         interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
  181         interconnect-names = "mdp0-mem";
  182 
  183         iommus = <&apps_smmu 0x420 0x2>,
  184                  <&apps_smmu 0x421 0x0>;
  185         ranges;
  186 
  187         mdss_mdp: display-controller@5e01000 {
  188                 compatible = "qcom,qcm2290-dpu";
  189                 reg = <0x05e01000 0x8f000>,
  190                       <0x05eb0000 0x2008>;
  191                 reg-names = "mdp", "vbif";
  192 
  193                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
  194                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
  195                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
  196                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
  197                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
  198                 clock-names = "bus", "iface", "core", "lut", "vsync";
  199 
  200                 operating-points-v2 = <&mdp_opp_table>;
  201                 power-domains = <&rpmpd QCM2290_VDDCX>;
  202 
  203                 interrupt-parent = <&mdss>;
  204                 interrupts = <0>;
  205 
  206                 ports {
  207                         #address-cells = <1>;
  208                         #size-cells = <0>;
  209 
  210                         port@0 {
  211                                 reg = <0>;
  212                                 dpu_intf1_out: endpoint {
  213                                         remote-endpoint = <&dsi0_in>;
  214                                 };
  215                         };
  216                 };
  217          };
  218     };
  219 ...

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