dsi-phy-10nm.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Qualcomm Display DSI 10nm PHY
    8 
    9 maintainers:
   10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
   11 
   12 allOf:
   13   - $ref: dsi-phy-common.yaml#
   14 
   15 properties:
   16   compatible:
   17     enum:
   18       - qcom,dsi-phy-10nm
   19       - qcom,dsi-phy-10nm-8998
   20 
   21   reg:
   22     items:
   23       - description: dsi phy register set
   24       - description: dsi phy lane register set
   25       - description: dsi pll register set
   26 
   27   reg-names:
   28     items:
   29       - const: dsi_phy
   30       - const: dsi_phy_lane
   31       - const: dsi_pll
   32 
   33   vdds-supply:
   34     description: |
   35       Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
   36       connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
   37 
   38   qcom,phy-rescode-offset-top:
   39     $ref: /schemas/types.yaml#/definitions/int8-array
   40     minItems: 5
   41     maxItems: 5
   42     description:
   43       Integer array of offset for pull-up legs rescode for all five lanes.
   44       To offset the drive strength from the calibrated value in an increasing
   45       manner, -32 is the weakest and +31 is the strongest.
   46     items:
   47       minimum: -32
   48       maximum: 31
   49 
   50   qcom,phy-rescode-offset-bot:
   51     $ref: /schemas/types.yaml#/definitions/int8-array
   52     minItems: 5
   53     maxItems: 5
   54     description:
   55       Integer array of offset for pull-down legs rescode for all five lanes.
   56       To offset the drive strength from the calibrated value in a decreasing
   57       manner, -32 is the weakest and +31 is the strongest.
   58     items:
   59       minimum: -32
   60       maximum: 31
   61 
   62   qcom,phy-drive-ldo-level:
   63     $ref: "/schemas/types.yaml#/definitions/uint32"
   64     description:
   65       The PHY LDO has an amplitude tuning feature to adjust the LDO output
   66       for the HSTX drive. Use supported levels (mV) to offset the drive level
   67       from the default value.
   68     enum: [ 375, 400, 425, 450, 475, 500 ]
   69 
   70 required:
   71   - compatible
   72   - reg
   73   - reg-names
   74   - vdds-supply
   75 
   76 unevaluatedProperties: false
   77 
   78 examples:
   79   - |
   80      #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
   81      #include <dt-bindings/clock/qcom,rpmh.h>
   82 
   83      dsi-phy@ae94400 {
   84          compatible = "qcom,dsi-phy-10nm";
   85          reg = <0x0ae94400 0x200>,
   86                <0x0ae94600 0x280>,
   87                <0x0ae94a00 0x1e0>;
   88          reg-names = "dsi_phy",
   89                      "dsi_phy_lane",
   90                      "dsi_pll";
   91 
   92          #clock-cells = <1>;
   93          #phy-cells = <0>;
   94 
   95          vdds-supply = <&vdda_mipi_dsi0_pll>;
   96          clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
   97                   <&rpmhcc RPMH_CXO_CLK>;
   98          clock-names = "iface", "ref";
   99 
  100          qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
  101          qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
  102          qcom,phy-drive-ldo-level = <400>;
  103      };
  104 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/display/msm/dsi-phy-10nm.yaml

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sys/contrib/device-tree/Bindings/display/msm/dsi-phy-10nm.yaml