lvds.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/panel/lvds.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: LVDS Display Panel
    8 
    9 maintainers:
   10   - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
   11   - Thierry Reding <thierry.reding@gmail.com>
   12 
   13 description: |+
   14   LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
   15   incompatible data link layers have been used over time to transmit image data
   16   to LVDS panels. This bindings supports display panels compatible with the
   17   following specifications.
   18 
   19   [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
   20   1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
   21   [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
   22   Semiconductor
   23   [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
   24   Electronics Standards Association (VESA)
   25 
   26   Device compatible with those specifications have been marketed under the
   27   FPD-Link and FlatLink brands.
   28 
   29 allOf:
   30   - $ref: panel-common.yaml#
   31 
   32 properties:
   33   compatible:
   34     contains:
   35       const: panel-lvds
   36     description:
   37       Shall contain "panel-lvds" in addition to a mandatory panel-specific
   38       compatible string defined in individual panel bindings. The "panel-lvds"
   39       value shall never be used on its own.
   40 
   41   data-mapping:
   42     enum:
   43       - jeida-18
   44       - jeida-24
   45       - vesa-24
   46     description: |
   47       The color signals mapping order.
   48 
   49       LVDS data mappings are defined as follows.
   50 
   51       - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
   52         [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
   53 
   54       Slot          0       1       2       3       4       5       6
   55                 ________________                         _________________
   56       Clock                     \_______________________/
   57                   ______  ______  ______  ______  ______  ______  ______
   58       DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
   59       DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
   60       DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
   61 
   62       - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
   63         specifications. Data are transferred as follows on 4 LVDS lanes.
   64 
   65       Slot          0       1       2       3       4       5       6
   66                 ________________                         _________________
   67       Clock                     \_______________________/
   68                   ______  ______  ______  ______  ______  ______  ______
   69       DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
   70       DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
   71       DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
   72       DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
   73 
   74       - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
   75         Data are transferred as follows on 4 LVDS lanes.
   76 
   77       Slot          0       1       2       3       4       5       6
   78                 ________________                         _________________
   79       Clock                     \_______________________/
   80                   ______  ______  ______  ______  ______  ______  ______
   81       DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
   82       DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
   83       DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
   84       DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
   85 
   86       Control signals are mapped as follows.
   87 
   88       CTL0: HSync
   89       CTL1: VSync
   90       CTL2: Data Enable
   91       CTL3: 0
   92 
   93   data-mirror:
   94     type: boolean
   95     description:
   96       If set, reverse the bit order described in the data mappings below on all
   97       data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
   98 
   99   port: true
  100   ports: true
  101 
  102 required:
  103   - compatible
  104   - data-mapping
  105   - width-mm
  106   - height-mm
  107   - panel-timing
  108 
  109 oneOf:
  110   - required:
  111       - port
  112   - required:
  113       - ports
  114 
  115 additionalProperties: true
  116 
  117 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/display/panel/lvds.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/panel/lvds.yaml