Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/renesas,du.txt
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1 * Renesas R-Car Display Unit (DU) 2 3 Required Properties: 4 5 - compatible: must be one of the following. 6 - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU 7 - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU 8 - "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU 9 - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU 10 - "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU 11 - "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU 12 - "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU 13 - "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU 14 - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU 15 - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU 16 - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU 17 - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU 18 - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU 19 - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU 20 - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU 21 - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU 22 - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU 23 - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU 24 - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU 25 - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU 26 - "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU 27 - "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU 28 - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU 29 30 - reg: the memory-mapped I/O registers base address and length 31 32 - interrupts: Interrupt specifiers for the DU interrupts. 33 34 - clocks: A list of phandles + clock-specifier pairs, one for each entry in 35 the clock-names property. 36 - clock-names: Name of the clocks. This property is model-dependent. 37 - R8A7779 uses a single functional clock. The clock doesn't need to be 38 named. 39 - All other DU instances use one functional clock per channel The 40 functional clocks must be named "du.x" with "x" being the channel 41 numerical index. 42 - In addition to the functional clocks, all DU versions also support 43 externally supplied pixel clocks. Those clocks are optional. When 44 supplied they must be named "dclkin.x" with "x" being the input clock 45 numerical index. 46 47 - renesas,cmms: A list of phandles to the CMM instances present in the SoC, 48 one for each available DU channel. The property shall not be specified for 49 SoCs that do not provide any CMM (such as V3M and V3H). 50 51 - renesas,vsps: A list of phandle and channel index tuples to the VSPs that 52 handle the memory interfaces for the DU channels. The phandle identifies the 53 VSP instance that serves the DU channel, and the channel index identifies 54 the LIF instance in that VSP. 55 56 Optional properties: 57 - resets: A list of phandle + reset-specifier pairs, one for each entry in 58 the reset-names property. 59 - reset-names: Names of the resets. This property is model-dependent. 60 - All but R8A7779 use one reset for a group of one or more successive 61 channels. The resets must be named "du.x" with "x" being the numerical 62 index of the lowest channel in the group. 63 64 Required nodes: 65 66 The connections to the DU output video ports are modeled using the OF graph 67 bindings specified in Documentation/devicetree/bindings/graph.txt. 68 69 The following table lists for each supported model the port number 70 corresponding to each DU output. 71 72 Port0 Port1 Port2 Port3 73 ----------------------------------------------------------------------------- 74 R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 - 75 R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - - 76 R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - - 77 R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - - 78 R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 - 79 R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 - 80 R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 - 81 R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 - 82 R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 - 83 R8A7779 (R-Car H1) DPAD 0 DPAD 1 - - 84 R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 - 85 R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - - 86 R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - - 87 R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - - 88 R8A7794 (R-Car E2) DPAD 0 DPAD 1 - - 89 R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0 90 R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 - 91 R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 - 92 R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 - 93 R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - - 94 R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - - 95 R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 - 96 R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 - 97 98 99 Example: R8A7795 (R-Car H3) ES2.0 DU 100 101 du: display@feb00000 { 102 compatible = "renesas,du-r8a7795"; 103 reg = <0 0xfeb00000 0 0x80000>; 104 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&cpg CPG_MOD 724>, 109 <&cpg CPG_MOD 723>, 110 <&cpg CPG_MOD 722>, 111 <&cpg CPG_MOD 721>; 112 clock-names = "du.0", "du.1", "du.2", "du.3"; 113 resets = <&cpg 724>, <&cpg 722>; 114 reset-names = "du.0", "du.2"; 115 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; 116 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; 117 118 ports { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 122 port@0 { 123 reg = <0>; 124 du_out_rgb: endpoint { 125 }; 126 }; 127 port@1 { 128 reg = <1>; 129 du_out_hdmi0: endpoint { 130 remote-endpoint = <&dw_hdmi0_in>; 131 }; 132 }; 133 port@2 { 134 reg = <2>; 135 du_out_hdmi1: endpoint { 136 remote-endpoint = <&dw_hdmi1_in>; 137 }; 138 }; 139 port@3 { 140 reg = <3>; 141 du_out_lvds0: endpoint { 142 }; 143 }; 144 }; 145 };
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