rockchip,dw-hdmi.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Rockchip DWC HDMI TX Encoder
    8 
    9 maintainers:
   10   - Mark Yao <markyao0591@gmail.com>
   11 
   12 description: |
   13   The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
   14   with a companion PHY IP.
   15 
   16 allOf:
   17   - $ref: ../bridge/synopsys,dw-hdmi.yaml#
   18 
   19 properties:
   20   compatible:
   21     enum:
   22       - rockchip,rk3228-dw-hdmi
   23       - rockchip,rk3288-dw-hdmi
   24       - rockchip,rk3328-dw-hdmi
   25       - rockchip,rk3399-dw-hdmi
   26       - rockchip,rk3568-dw-hdmi
   27 
   28   reg-io-width:
   29     const: 4
   30 
   31   avdd-0v9-supply:
   32     description:
   33       A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
   34       varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
   35       HDMI_AVDD_1V0.
   36 
   37   avdd-1v8-supply:
   38     description:
   39       A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
   40       SoC usually is HDMI_TX_AVDD_1V8.
   41 
   42   clocks:
   43     minItems: 2
   44     items:
   45       - {}
   46       - {}
   47       # The next three clocks are all optional, but shall be specified in this
   48       # order when present.
   49       - description: The HDMI CEC controller main clock
   50       - description: Power for GRF IO
   51       - description: External clock for some HDMI PHY (old clock name, deprecated)
   52       - description: External clock for some HDMI PHY (new name)
   53 
   54   clock-names:
   55     minItems: 2
   56     items:
   57       - {}
   58       - {}
   59       - enum:
   60           - cec
   61           - grf
   62           - vpll
   63           - ref
   64       - enum:
   65           - grf
   66           - vpll
   67           - ref
   68       - enum:
   69           - vpll
   70           - ref
   71 
   72   ddc-i2c-bus:
   73     $ref: /schemas/types.yaml#/definitions/phandle
   74     description:
   75       The HDMI DDC bus can be connected to either a system I2C master or the
   76       functionally-reduced I2C master contained in the DWC HDMI. When connected
   77       to a system I2C master this property contains a phandle to that I2C
   78       master controller.
   79 
   80   phys:
   81     maxItems: 1
   82     description: The HDMI PHY
   83 
   84   phy-names:
   85     const: hdmi
   86 
   87   pinctrl-names:
   88     description:
   89       The unwedge pinctrl entry shall drive the DDC SDA line low. This is
   90       intended to work around a hardware errata that can cause the DDC I2C
   91       bus to be wedged.
   92     minItems: 1
   93     items:
   94       - const: default
   95       - const: unwedge
   96 
   97   ports:
   98     $ref: /schemas/graph.yaml#/properties/ports
   99 
  100     patternProperties:
  101       "^port(@0)?$":
  102         $ref: /schemas/graph.yaml#/properties/port
  103         description: Input of the DWC HDMI TX
  104         properties:
  105           endpoint:
  106             description: Connection to the VOP
  107           endpoint@0:
  108             description: Connection to the VOPB
  109           endpoint@1:
  110             description: Connection to the VOPL
  111     properties:
  112       port@1:
  113         $ref: /schemas/graph.yaml#/properties/port
  114         description: Output of the DWC HDMI TX
  115 
  116   rockchip,grf:
  117     $ref: /schemas/types.yaml#/definitions/phandle
  118     description:
  119       phandle to the GRF to mux vopl/vopb.
  120 
  121 required:
  122   - compatible
  123   - reg
  124   - reg-io-width
  125   - clocks
  126   - clock-names
  127   - interrupts
  128   - ports
  129   - rockchip,grf
  130 
  131 unevaluatedProperties: false
  132 
  133 examples:
  134   - |
  135     #include <dt-bindings/clock/rk3288-cru.h>
  136     #include <dt-bindings/interrupt-controller/arm-gic.h>
  137     #include <dt-bindings/interrupt-controller/irq.h>
  138 
  139     hdmi: hdmi@ff980000 {
  140         compatible = "rockchip,rk3288-dw-hdmi";
  141         reg = <0xff980000 0x20000>;
  142         reg-io-width = <4>;
  143         ddc-i2c-bus = <&i2c5>;
  144         rockchip,grf = <&grf>;
  145         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  146         clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
  147         clock-names = "iahb", "isfr";
  148 
  149         ports {
  150             port {
  151                 #address-cells = <1>;
  152                 #size-cells = <0>;
  153 
  154                 hdmi_in_vopb: endpoint@0 {
  155                     reg = <0>;
  156                     remote-endpoint = <&vopb_out_hdmi>;
  157                 };
  158                 hdmi_in_vopl: endpoint@1 {
  159                     reg = <1>;
  160                     remote-endpoint = <&vopl_out_hdmi>;
  161                 };
  162             };
  163         };
  164     };
  165 
  166 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/display/rockchip/rockchip,dw-hdmi.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/rockchip/rockchip,dw-hdmi.yaml