1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA Tegra186 (and later) Display Controller
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13 properties:
14 $nodename:
15 pattern: "^display@[0-9a-f]+$"
16
17 compatible:
18 enum:
19 - nvidia,tegra186-dc
20 - nvidia,tegra194-dc
21
22 reg:
23 maxItems: 1
24
25 interrupts:
26 maxItems: 1
27
28 clocks:
29 items:
30 - description: display controller pixel clock
31
32 clock-names:
33 items:
34 - const: dc
35
36 resets:
37 items:
38 - description: display controller reset
39
40 reset-names:
41 items:
42 - const: dc
43
44 power-domains:
45 maxItems: 1
46
47 iommus:
48 maxItems: 1
49
50 interconnects:
51 description: Description of the interconnect paths for the
52 display controller; see ../interconnect/interconnect.txt
53 for details.
54
55 interconnect-names:
56 items:
57 - const: dma-mem # read-0
58 - const: read-1
59
60 nvidia,outputs:
61 description: A list of phandles of outputs that this display
62 controller can drive.
63 $ref: "/schemas/types.yaml#/definitions/phandle-array"
64
65 nvidia,head:
66 description: The number of the display controller head. This
67 is used to setup the various types of output to receive
68 video data from the given head.
69 $ref: "/schemas/types.yaml#/definitions/uint32"
70
71 additionalProperties: false
72
73 required:
74 - compatible
75 - reg
76 - interrupts
77 - clocks
78 - clock-names
79 - resets
80 - reset-names
81 - power-domains
82 - nvidia,outputs
83 - nvidia,head
84
85 # see nvidia,tegra186-display.yaml for examples
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