nvidia,tegra186-display.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: NVIDIA Tegra186 (and later) Display Hub
    8 
    9 maintainers:
   10   - Thierry Reding <thierry.reding@gmail.com>
   11   - Jon Hunter <jonathanh@nvidia.com>
   12 
   13 properties:
   14   $nodename:
   15     pattern: "^display-hub@[0-9a-f]+$"
   16 
   17   compatible:
   18     enum:
   19       - nvidia,tegra186-display
   20       - nvidia,tegra194-display
   21 
   22   '#address-cells':
   23     const: 1
   24 
   25   '#size-cells':
   26     const: 1
   27 
   28   reg:
   29     maxItems: 1
   30 
   31   interrupts:
   32     maxItems: 1
   33 
   34   clocks:
   35     minItems: 2
   36     maxItems: 3
   37 
   38   clock-names:
   39     minItems: 2
   40     maxItems: 3
   41 
   42   resets:
   43     items:
   44       - description: display hub reset
   45       - description: window group 0 reset
   46       - description: window group 1 reset
   47       - description: window group 2 reset
   48       - description: window group 3 reset
   49       - description: window group 4 reset
   50       - description: window group 5 reset
   51 
   52   reset-names:
   53     items:
   54       - const: misc
   55       - const: wgrp0
   56       - const: wgrp1
   57       - const: wgrp2
   58       - const: wgrp3
   59       - const: wgrp4
   60       - const: wgrp5
   61 
   62   power-domains:
   63     maxItems: 1
   64 
   65   ranges:
   66     maxItems: 1
   67 
   68 patternProperties:
   69   "^display@[0-9a-f]+$":
   70     type: object
   71 
   72 allOf:
   73   - if:
   74       properties:
   75         compatible:
   76           contains:
   77             const: nvidia,tegra186-display
   78     then:
   79       properties:
   80         clocks:
   81           items:
   82             - description: display core clock
   83             - description: display stream compression clock
   84             - description: display hub clock
   85 
   86         clock-names:
   87           items:
   88             - const: disp
   89             - const: dsc
   90             - const: hub
   91     else:
   92       properties:
   93         clocks:
   94           items:
   95             - description: display core clock
   96             - description: display hub clock
   97 
   98         clock-names:
   99           items:
  100             - const: disp
  101             - const: hub
  102 
  103 additionalProperties: false
  104 
  105 required:
  106   - compatible
  107   - reg
  108   - clocks
  109   - clock-names
  110   - resets
  111   - reset-names
  112   - power-domains
  113   - "#address-cells"
  114   - "#size-cells"
  115   - ranges
  116 
  117 examples:
  118   - |
  119     #include <dt-bindings/clock/tegra186-clock.h>
  120     #include <dt-bindings/interrupt-controller/arm-gic.h>
  121     #include <dt-bindings/memory/tegra186-mc.h>
  122     #include <dt-bindings/power/tegra186-powergate.h>
  123     #include <dt-bindings/reset/tegra186-reset.h>
  124 
  125     display-hub@15200000 {
  126         compatible = "nvidia,tegra186-display";
  127         reg = <0x15200000 0x00040000>;
  128         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
  129                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
  130                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
  131                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
  132                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
  133                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
  134                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
  135         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
  136                       "wgrp3", "wgrp4", "wgrp5";
  137         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
  138                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
  139                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
  140         clock-names = "disp", "dsc", "hub";
  141         status = "disabled";
  142 
  143         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
  144 
  145         #address-cells = <1>;
  146         #size-cells = <1>;
  147 
  148         ranges = <0x15200000 0x15200000 0x40000>;
  149 
  150         display@15200000 {
  151             compatible = "nvidia,tegra186-dc";
  152             reg = <0x15200000 0x10000>;
  153             interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  154             clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
  155             clock-names = "dc";
  156             resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
  157             reset-names = "dc";
  158 
  159             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
  160             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
  161                             <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  162             interconnect-names = "dma-mem", "read-1";
  163             iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
  164 
  165             nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
  166             nvidia,head = <0>;
  167         };
  168 
  169         display@15210000 {
  170             compatible = "nvidia,tegra186-dc";
  171             reg = <0x15210000 0x10000>;
  172             interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  173             clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
  174             clock-names = "dc";
  175             resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
  176             reset-names = "dc";
  177 
  178             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
  179             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
  180                             <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  181             interconnect-names = "dma-mem", "read-1";
  182             iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
  183 
  184             nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
  185             nvidia,head = <1>;
  186         };
  187 
  188         display@15220000 {
  189             compatible = "nvidia,tegra186-dc";
  190             reg = <0x15220000 0x10000>;
  191             interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  192             clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
  193             clock-names = "dc";
  194             resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
  195             reset-names = "dc";
  196 
  197             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
  198             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
  199                             <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  200             interconnect-names = "dma-mem", "read-1";
  201             iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
  202 
  203             nvidia,outputs = <&sor0 &sor1>;
  204             nvidia,head = <2>;
  205         };
  206     };
  207 
  208   - |
  209     #include <dt-bindings/clock/tegra194-clock.h>
  210     #include <dt-bindings/interrupt-controller/arm-gic.h>
  211     #include <dt-bindings/memory/tegra194-mc.h>
  212     #include <dt-bindings/power/tegra194-powergate.h>
  213     #include <dt-bindings/reset/tegra194-reset.h>
  214 
  215     display-hub@15200000 {
  216         compatible = "nvidia,tegra194-display";
  217         reg = <0x15200000 0x00040000>;
  218         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
  219                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
  220                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
  221                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
  222                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
  223                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
  224                  <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
  225         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
  226                       "wgrp3", "wgrp4", "wgrp5";
  227         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
  228                  <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
  229         clock-names = "disp", "hub";
  230         status = "disabled";
  231 
  232         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
  233 
  234         #address-cells = <1>;
  235         #size-cells = <1>;
  236 
  237         ranges = <0x15200000 0x15200000 0x40000>;
  238 
  239         display@15200000 {
  240             compatible = "nvidia,tegra194-dc";
  241             reg = <0x15200000 0x10000>;
  242             interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  243             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
  244             clock-names = "dc";
  245             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
  246             reset-names = "dc";
  247 
  248             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
  249             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
  250                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  251             interconnect-names = "dma-mem", "read-1";
  252 
  253             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
  254             nvidia,head = <0>;
  255         };
  256 
  257         display@15210000 {
  258             compatible = "nvidia,tegra194-dc";
  259             reg = <0x15210000 0x10000>;
  260             interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  261             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
  262             clock-names = "dc";
  263             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
  264             reset-names = "dc";
  265 
  266             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
  267             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
  268                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  269             interconnect-names = "dma-mem", "read-1";
  270 
  271             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
  272             nvidia,head = <1>;
  273         };
  274 
  275         display@15220000 {
  276             compatible = "nvidia,tegra194-dc";
  277             reg = <0x15220000 0x10000>;
  278             interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  279             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
  280             clock-names = "dc";
  281             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
  282             reset-names = "dc";
  283 
  284             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
  285             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
  286                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  287             interconnect-names = "dma-mem", "read-1";
  288 
  289             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
  290             nvidia,head = <2>;
  291         };
  292 
  293         display@15230000 {
  294             compatible = "nvidia,tegra194-dc";
  295             reg = <0x15230000 0x10000>;
  296             interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
  297             clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
  298             clock-names = "dc";
  299             resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
  300             reset-names = "dc";
  301 
  302             power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
  303             interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
  304                             <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
  305             interconnect-names = "dma-mem", "read-1";
  306 
  307             nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
  308             nvidia,head = <3>;
  309         };
  310     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra186-display.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra186-display.yaml