1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NVIDIA 2D graphics engine
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13 properties:
14 $nodename:
15 pattern: "^gr2d@[0-9a-f]+$"
16
17 compatible:
18 enum:
19 - nvidia,tegra20-gr2d
20 - nvidia,tegra30-gr2d
21 - nvidia,tegra114-gr2d
22
23 reg:
24 maxItems: 1
25
26 interrupts:
27 maxItems: 1
28
29 clocks:
30 items:
31 - description: module clock
32
33 resets:
34 items:
35 - description: module reset
36 - description: memory client hotflush reset
37
38 reset-names:
39 items:
40 - const: 2d
41 - const: mc
42
43 iommus:
44 maxItems: 1
45
46 interconnects:
47 maxItems: 4
48
49 interconnect-names:
50 maxItems: 4
51
52 operating-points-v2:
53 $ref: "/schemas/types.yaml#/definitions/phandle"
54
55 power-domains:
56 items:
57 - description: phandle to the HEG or core power domain
58
59 additionalProperties: false
60
61 examples:
62 - |
63 #include <dt-bindings/clock/tegra20-car.h>
64 #include <dt-bindings/interrupt-controller/arm-gic.h>
65 #include <dt-bindings/memory/tegra20-mc.h>
66
67 gr2d@54140000 {
68 compatible = "nvidia,tegra20-gr2d";
69 reg = <0x54140000 0x00040000>;
70 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
72 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
73 reset-names = "2d", "mc";
74 };
Cache object: fbe8f1947eb01e8cb0cdfc434c77af8f
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