Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/display/tegra/nvidia,tegra20-host1x.txt
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1 NVIDIA Tegra host1x 2 3 Required properties: 4 - compatible: "nvidia,tegra<chip>-host1x" 5 - reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10 - interrupts: The interrupt outputs from the controller. 11 - #address-cells: The number of cells used to represent physical base addresses 12 in the host1x address space. Should be 1. 13 - #size-cells: The number of cells used to represent the size of an address 14 range in the host1x address space. Should be 1. 15 - ranges: The mapping of the host1x address space to the CPU address space. 16 - clocks: Must contain one entry, for the module clock. 17 See ../clocks/clock-bindings.txt for details. 18 - resets: Must contain an entry for each entry in reset-names. 19 See ../reset/reset.txt for details. 20 - reset-names: Must include the following entries: 21 - host1x 22 - mc 23 24 Optional properties: 25 - operating-points-v2: See ../bindings/opp/opp.txt for details. 26 - power-domains: Phandle to HEG or core power domain. 27 28 For each opp entry in 'operating-points-v2' table of host1x and its modules: 29 - opp-supported-hw: One bitfield indicating: 30 On Tegra20: SoC process ID mask 31 On Tegra30+: SoC speedo ID mask 32 33 A bitwise AND is performed against the value and if any bit 34 matches, the OPP gets enabled. 35 36 Each host1x client module having to perform DMA through the Memory Controller 37 should have the interconnect endpoints set to the Memory Client and External 38 Memory respectively. 39 40 The host1x top-level node defines a number of children, each representing one 41 of the following host1x client modules: 42 43 - mpe: video encoder 44 45 Required properties: 46 - compatible: "nvidia,tegra<chip>-mpe" 47 - reg: Physical base address and length of the controller's registers. 48 - interrupts: The interrupt outputs from the controller. 49 - clocks: Must contain one entry, for the module clock. 50 See ../clocks/clock-bindings.txt for details. 51 - resets: Must contain an entry for each entry in reset-names. 52 See ../reset/reset.txt for details. 53 - reset-names: Must include the following entries: 54 - mpe 55 56 Optional properties: 57 - interconnects: Must contain entry for the MPE memory clients. 58 - interconnect-names: Must include name of the interconnect path for each 59 interconnect entry. Consult TRM documentation for information about 60 available memory clients, see MEMORY CONTROLLER section. 61 - operating-points-v2: See ../bindings/opp/opp.txt for details. 62 - power-domains: Phandle to MPE power domain. 63 64 - vi: video input 65 66 Required properties: 67 - compatible: "nvidia,tegra<chip>-vi" 68 - reg: Physical base address and length of the controller registers. 69 - interrupts: The interrupt outputs from the controller. 70 - clocks: clocks: Must contain one entry, for the module clock. 71 See ../clocks/clock-bindings.txt for details. 72 - Tegra20/Tegra30/Tegra114/Tegra124: 73 - resets: Must contain an entry for each entry in reset-names. 74 See ../reset/reset.txt for details. 75 - reset-names: Must include the following entries: 76 - vi 77 - Tegra210: 78 - power-domains: Must include venc powergate node as vi is in VE partition. 79 80 ports (optional node) 81 vi can have optional ports node and max 6 ports are supported. Each port 82 should have single 'endpoint' child node. All port nodes are grouped under 83 ports node. Please refer to the bindings defined in 84 Documentation/devicetree/bindings/media/video-interfaces.txt 85 86 csi (required node) 87 Tegra210 has CSI part of VI sharing same host interface and register space. 88 So, VI device node should have CSI child node. 89 90 - csi: mipi csi interface to vi 91 92 Required properties: 93 - compatible: "nvidia,tegra210-csi" 94 - reg: Physical base address offset to parent and length of the controller 95 registers. 96 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. 97 See ../clocks/clock-bindings.txt for details. 98 - power-domains: Must include sor powergate node as csicil is in 99 SOR partition. 100 101 channel (optional nodes) 102 Maximum 6 channels are supported with each csi brick as either x4 or x2 103 based on hw connectivity to sensor. 104 105 Required properties: 106 - reg: csi port number. Valid port numbers are 0 through 5. 107 - nvidia,mipi-calibrate: Should contain a phandle and a specifier 108 specifying which pads are used by this CSI port and need to be 109 calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. 110 111 Each channel node must contain 2 port nodes which can be grouped 112 under 'ports' node and each port should have a single child 'endpoint' 113 node. 114 115 ports node 116 Please refer to the bindings defined in 117 Documentation/devicetree/bindings/media/video-interfaces.txt 118 119 ports node must contain below 2 port nodes. 120 port@0 with single child 'endpoint' node always a sink. 121 port@1 with single child 'endpoint' node always a source. 122 123 port@0 (required node) 124 Required properties: 125 - reg: 0 126 127 endpoint (required node) 128 Required properties: 129 - data-lanes: an array of data lane from 1 to 8. Valid array 130 lengths are 1/2/4/8. 131 - remote-endpoint: phandle to sensor 'endpoint' node. 132 133 port@1 (required node) 134 Required properties: 135 - reg: 1 136 137 endpoint (required node) 138 Required properties: 139 - remote-endpoint: phandle to vi port 'endpoint' node. 140 141 Optional properties: 142 - interconnects: Must contain entry for the VI memory clients. 143 - interconnect-names: Must include name of the interconnect path for each 144 interconnect entry. Consult TRM documentation for information about 145 available memory clients, see MEMORY CONTROLLER section. 146 - operating-points-v2: See ../bindings/opp/opp.txt for details. 147 - power-domains: Phandle to VENC power domain. 148 149 - epp: encoder pre-processor 150 151 Required properties: 152 - compatible: "nvidia,tegra<chip>-epp" 153 - reg: Physical base address and length of the controller's registers. 154 - interrupts: The interrupt outputs from the controller. 155 - clocks: Must contain one entry, for the module clock. 156 See ../clocks/clock-bindings.txt for details. 157 - resets: Must contain an entry for each entry in reset-names. 158 See ../reset/reset.txt for details. 159 - reset-names: Must include the following entries: 160 - epp 161 162 Optional properties: 163 - interconnects: Must contain entry for the EPP memory clients. 164 - interconnect-names: Must include name of the interconnect path for each 165 interconnect entry. Consult TRM documentation for information about 166 available memory clients, see MEMORY CONTROLLER section. 167 - operating-points-v2: See ../bindings/opp/opp.txt for details. 168 - power-domains: Phandle to HEG or core power domain. 169 170 - isp: image signal processor 171 172 Required properties: 173 - compatible: "nvidia,tegra<chip>-isp" 174 - reg: Physical base address and length of the controller's registers. 175 - interrupts: The interrupt outputs from the controller. 176 - clocks: Must contain one entry, for the module clock. 177 See ../clocks/clock-bindings.txt for details. 178 - resets: Must contain an entry for each entry in reset-names. 179 See ../reset/reset.txt for details. 180 - reset-names: Must include the following entries: 181 - isp 182 183 Optional properties: 184 - interconnects: Must contain entry for the ISP memory clients. 185 - interconnect-names: Must include name of the interconnect path for each 186 interconnect entry. Consult TRM documentation for information about 187 available memory clients, see MEMORY CONTROLLER section. 188 - power-domains: Phandle to VENC or core power domain. 189 190 - gr2d: 2D graphics engine 191 192 Required properties: 193 - compatible: "nvidia,tegra<chip>-gr2d" 194 - reg: Physical base address and length of the controller's registers. 195 - interrupts: The interrupt outputs from the controller. 196 - clocks: Must contain one entry, for the module clock. 197 See ../clocks/clock-bindings.txt for details. 198 - resets: Must contain an entry for each entry in reset-names. 199 See ../reset/reset.txt for details. 200 - reset-names: Must include the following entries: 201 - 2d 202 - mc 203 204 Optional properties: 205 - interconnects: Must contain entry for the GR2D memory clients. 206 - interconnect-names: Must include name of the interconnect path for each 207 interconnect entry. Consult TRM documentation for information about 208 available memory clients, see MEMORY CONTROLLER section. 209 - operating-points-v2: See ../bindings/opp/opp.txt for details. 210 - power-domains: Phandle to HEG or core power domain. 211 212 - gr3d: 3D graphics engine 213 214 Required properties: 215 - compatible: "nvidia,tegra<chip>-gr3d" 216 - reg: Physical base address and length of the controller's registers. 217 - clocks: Must contain an entry for each entry in clock-names. 218 See ../clocks/clock-bindings.txt for details. 219 - clock-names: Must include the following entries: 220 (This property may be omitted if the only clock in the list is "3d") 221 - 3d 222 This MUST be the first entry. 223 - 3d2 (Only required on SoCs with two 3D clocks) 224 - resets: Must contain an entry for each entry in reset-names. 225 See ../reset/reset.txt for details. 226 - reset-names: Must include the following entries: 227 - 3d 228 - 3d2 (Only required on SoCs with two 3D clocks) 229 - mc 230 - mc2 (Only required on SoCs with two 3D clocks) 231 232 Optional properties: 233 - interconnects: Must contain entry for the GR3D memory clients. 234 - interconnect-names: Must include name of the interconnect path for each 235 interconnect entry. Consult TRM documentation for information about 236 available memory clients, see MEMORY CONTROLLER section. 237 - operating-points-v2: See ../bindings/opp/opp.txt for details. 238 - power-domains: Phandles to 3D or core power domain. 239 240 - dc: display controller 241 242 Required properties: 243 - compatible: "nvidia,tegra<chip>-dc" 244 - reg: Physical base address and length of the controller's registers. 245 - interrupts: The interrupt outputs from the controller. 246 - clocks: Must contain an entry for each entry in clock-names. 247 See ../clocks/clock-bindings.txt for details. 248 - clock-names: Must include the following entries: 249 - dc 250 This MUST be the first entry. 251 - parent 252 - resets: Must contain an entry for each entry in reset-names. 253 See ../reset/reset.txt for details. 254 - reset-names: Must include the following entries: 255 - dc 256 - nvidia,head: The number of the display controller head. This is used to 257 setup the various types of output to receive video data from the given 258 head. 259 260 Each display controller node has a child node, named "rgb", that represents 261 the RGB output associated with the controller. It can take the following 262 optional properties: 263 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 264 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 265 - nvidia,edid: supplies a binary EDID blob 266 - nvidia,panel: phandle of a display panel 267 - interconnects: Must contain entry for the DC memory clients. 268 - interconnect-names: Must include name of the interconnect path for each 269 interconnect entry. Consult TRM documentation for information about 270 available memory clients, see MEMORY CONTROLLER section. 271 - operating-points-v2: See ../bindings/opp/opp.txt for details. 272 - power-domains: Phandle to core power domain. 273 274 - hdmi: High Definition Multimedia Interface 275 276 Required properties: 277 - compatible: "nvidia,tegra<chip>-hdmi" 278 - reg: Physical base address and length of the controller's registers. 279 - interrupts: The interrupt outputs from the controller. 280 - hdmi-supply: supply for the +5V HDMI connector pin 281 - vdd-supply: regulator for supply voltage 282 - pll-supply: regulator for PLL 283 - clocks: Must contain an entry for each entry in clock-names. 284 See ../clocks/clock-bindings.txt for details. 285 - clock-names: Must include the following entries: 286 - hdmi 287 This MUST be the first entry. 288 - parent 289 - resets: Must contain an entry for each entry in reset-names. 290 See ../reset/reset.txt for details. 291 - reset-names: Must include the following entries: 292 - hdmi 293 294 Optional properties: 295 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 296 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 297 - nvidia,edid: supplies a binary EDID blob 298 - nvidia,panel: phandle of a display panel 299 - operating-points-v2: See ../bindings/opp/opp.txt for details. 300 301 - tvo: TV encoder output 302 303 Required properties: 304 - compatible: "nvidia,tegra<chip>-tvo" 305 - reg: Physical base address and length of the controller's registers. 306 - interrupts: The interrupt outputs from the controller. 307 - clocks: Must contain one entry, for the module clock. 308 See ../clocks/clock-bindings.txt for details. 309 310 Optional properties: 311 - operating-points-v2: See ../bindings/opp/opp.txt for details. 312 - power-domains: Phandle to core power domain. 313 314 - dsi: display serial interface 315 316 Required properties: 317 - compatible: "nvidia,tegra<chip>-dsi" 318 - reg: Physical base address and length of the controller's registers. 319 - clocks: Must contain an entry for each entry in clock-names. 320 See ../clocks/clock-bindings.txt for details. 321 - clock-names: Must include the following entries: 322 - dsi 323 This MUST be the first entry. 324 - lp 325 - parent 326 - resets: Must contain an entry for each entry in reset-names. 327 See ../reset/reset.txt for details. 328 - reset-names: Must include the following entries: 329 - dsi 330 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 331 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 332 which pads are used by this DSI output and need to be calibrated. See also 333 ../display/tegra/nvidia,tegra114-mipi.txt. 334 335 Optional properties: 336 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 337 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 338 - nvidia,edid: supplies a binary EDID blob 339 - nvidia,panel: phandle of a display panel 340 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 341 up with in order to support up to 8 data lanes 342 - operating-points-v2: See ../bindings/opp/opp.txt for details. 343 344 - sor: serial output resource 345 346 Required properties: 347 - compatible: Should be: 348 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 349 - "nvidia,tegra132-sor": for Tegra132 350 - "nvidia,tegra210-sor": for Tegra210 351 - "nvidia,tegra210-sor1": for Tegra210 352 - "nvidia,tegra186-sor": for Tegra186 353 - "nvidia,tegra186-sor1": for Tegra186 354 - reg: Physical base address and length of the controller's registers. 355 - interrupts: The interrupt outputs from the controller. 356 - clocks: Must contain an entry for each entry in clock-names. 357 See ../clocks/clock-bindings.txt for details. 358 - clock-names: Must include the following entries: 359 - sor: clock input for the SOR hardware 360 - out: SOR output clock 361 - parent: input for the pixel clock 362 - dp: reference clock for the SOR clock 363 - safe: safe reference for the SOR clock during power up 364 365 For Tegra186 and later: 366 - pad: SOR pad output clock (on Tegra186 and later) 367 368 Obsolete: 369 - source: source clock for the SOR clock (obsolete, use "out" instead) 370 371 - resets: Must contain an entry for each entry in reset-names. 372 See ../reset/reset.txt for details. 373 - reset-names: Must include the following entries: 374 - sor 375 376 Required properties on Tegra186 and later: 377 - nvidia,interface: index of the SOR interface 378 379 Optional properties: 380 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 381 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 382 - nvidia,edid: supplies a binary EDID blob 383 - nvidia,panel: phandle of a display panel 384 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane 385 of the SOR, identified by the cell's index, is mapped via the crossbar to 386 the pad specified by the cell's value. 387 388 Optional properties when driving an eDP output: 389 - nvidia,dpaux: phandle to a DispayPort AUX interface 390 391 - dpaux: DisplayPort AUX interface 392 - compatible : Should contain one of the following: 393 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 394 - "nvidia,tegra210-dpaux": for Tegra210 395 - reg: Physical base address and length of the controller's registers. 396 - interrupts: The interrupt outputs from the controller. 397 - clocks: Must contain an entry for each entry in clock-names. 398 See ../clocks/clock-bindings.txt for details. 399 - clock-names: Must include the following entries: 400 - dpaux: clock input for the DPAUX hardware 401 - parent: reference clock 402 - resets: Must contain an entry for each entry in reset-names. 403 See ../reset/reset.txt for details. 404 - reset-names: Must include the following entries: 405 - dpaux 406 - vdd-supply: phandle of a supply that powers the DisplayPort link 407 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 408 must be always present. If there are no I2C slave devices, an empty 409 node should be added. See ../../i2c/i2c.txt for more information. 410 411 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 412 regarding the DPAUX pad controller bindings. 413 414 - vic: Video Image Compositor 415 - compatible : "nvidia,tegra<chip>-vic" 416 - reg: Physical base address and length of the controller's registers. 417 - interrupts: The interrupt outputs from the controller. 418 - clocks: Must contain an entry for each entry in clock-names. 419 See ../clocks/clock-bindings.txt for details. 420 - clock-names: Must include the following entries: 421 - vic: clock input for the VIC hardware 422 - resets: Must contain an entry for each entry in reset-names. 423 See ../reset/reset.txt for details. 424 - reset-names: Must include the following entries: 425 - vic 426 427 Optional properties: 428 - interconnects: Must contain entry for the VIC memory clients. 429 - interconnect-names: Must include name of the interconnect path for each 430 interconnect entry. Consult TRM documentation for information about 431 available memory clients, see MEMORY CONTROLLER section. 432 433 Example: 434 435 / { 436 ... 437 438 host1x { 439 compatible = "nvidia,tegra20-host1x", "simple-bus"; 440 reg = <0x50000000 0x00024000>; 441 interrupts = <0 65 0x04 /* mpcore syncpt */ 442 0 67 0x04>; /* mpcore general */ 443 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 444 resets = <&tegra_car 28>; 445 reset-names = "host1x"; 446 operating-points-v2 = <&dvfs_opp_table>; 447 power-domains = <&domain>; 448 449 #address-cells = <1>; 450 #size-cells = <1>; 451 452 ranges = <0x54000000 0x54000000 0x04000000>; 453 454 mpe { 455 compatible = "nvidia,tegra20-mpe"; 456 reg = <0x54040000 0x00040000>; 457 interrupts = <0 68 0x04>; 458 clocks = <&tegra_car TEGRA20_CLK_MPE>; 459 resets = <&tegra_car 60>; 460 reset-names = "mpe"; 461 operating-points-v2 = <&dvfs_opp_table>; 462 power-domains = <&domain>; 463 }; 464 465 vi@54080000 { 466 compatible = "nvidia,tegra210-vi"; 467 reg = <0x0 0x54080000 0x0 0x700>; 468 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 469 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 470 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 471 operating-points-v2 = <&dvfs_opp_table>; 472 473 clocks = <&tegra_car TEGRA210_CLK_VI>; 474 power-domains = <&pd_venc>; 475 476 #address-cells = <1>; 477 #size-cells = <1>; 478 479 ranges = <0x0 0x0 0x54080000 0x2000>; 480 481 ports { 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 port@0 { 486 reg = <0>; 487 imx219_vi_in0: endpoint { 488 remote-endpoint = <&imx219_csi_out0>; 489 }; 490 }; 491 }; 492 493 csi@838 { 494 compatible = "nvidia,tegra210-csi"; 495 reg = <0x838 0x1300>; 496 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 497 <&tegra_car TEGRA210_CLK_CILCD>, 498 <&tegra_car TEGRA210_CLK_CILE>, 499 <&tegra_car TEGRA210_CLK_CSI_TPG>; 500 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 501 <&tegra_car TEGRA210_CLK_PLL_P>, 502 <&tegra_car TEGRA210_CLK_PLL_P>; 503 assigned-clock-rates = <102000000>, 504 <102000000>, 505 <102000000>, 506 <972000000>; 507 508 clocks = <&tegra_car TEGRA210_CLK_CSI>, 509 <&tegra_car TEGRA210_CLK_CILAB>, 510 <&tegra_car TEGRA210_CLK_CILCD>, 511 <&tegra_car TEGRA210_CLK_CILE>, 512 <&tegra_car TEGRA210_CLK_CSI_TPG>; 513 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 514 power-domains = <&pd_sor>; 515 516 #address-cells = <1>; 517 #size-cells = <0>; 518 519 channel@0 { 520 reg = <0>; 521 nvidia,mipi-calibrate = <&mipi 0x001>; 522 523 ports { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 527 port@0 { 528 reg = <0>; 529 imx219_csi_in0: endpoint { 530 data-lanes = <1 2>; 531 remote-endpoint = <&imx219_out0>; 532 }; 533 }; 534 535 port@1 { 536 reg = <1>; 537 imx219_csi_out0: endpoint { 538 remote-endpoint = <&imx219_vi_in0>; 539 }; 540 }; 541 }; 542 }; 543 }; 544 }; 545 546 epp { 547 compatible = "nvidia,tegra20-epp"; 548 reg = <0x540c0000 0x00040000>; 549 interrupts = <0 70 0x04>; 550 clocks = <&tegra_car TEGRA20_CLK_EPP>; 551 resets = <&tegra_car 19>; 552 reset-names = "epp"; 553 operating-points-v2 = <&dvfs_opp_table>; 554 power-domains = <&domain>; 555 }; 556 557 isp { 558 compatible = "nvidia,tegra20-isp"; 559 reg = <0x54100000 0x00040000>; 560 interrupts = <0 71 0x04>; 561 clocks = <&tegra_car TEGRA20_CLK_ISP>; 562 resets = <&tegra_car 23>; 563 reset-names = "isp"; 564 }; 565 566 gr2d { 567 compatible = "nvidia,tegra20-gr2d"; 568 reg = <0x54140000 0x00040000>; 569 interrupts = <0 72 0x04>; 570 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 571 resets = <&tegra_car 21>; 572 reset-names = "2d"; 573 operating-points-v2 = <&dvfs_opp_table>; 574 power-domains = <&domain>; 575 }; 576 577 gr3d { 578 compatible = "nvidia,tegra20-gr3d"; 579 reg = <0x54180000 0x00040000>; 580 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 581 resets = <&tegra_car 24>; 582 reset-names = "3d"; 583 operating-points-v2 = <&dvfs_opp_table>; 584 power-domains = <&domain>; 585 }; 586 587 dc@54200000 { 588 compatible = "nvidia,tegra20-dc"; 589 reg = <0x54200000 0x00040000>; 590 interrupts = <0 73 0x04>; 591 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 592 <&tegra_car TEGRA20_CLK_PLL_P>; 593 clock-names = "dc", "parent"; 594 resets = <&tegra_car 27>; 595 reset-names = "dc"; 596 operating-points-v2 = <&dvfs_opp_table>; 597 power-domains = <&domain>; 598 599 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, 600 <&mc TEGRA20_MC_DISPLAY0B &emc>, 601 <&mc TEGRA20_MC_DISPLAY0C &emc>, 602 <&mc TEGRA20_MC_DISPLAYHC &emc>; 603 interconnect-names = "wina", 604 "winb", 605 "winc", 606 "cursor"; 607 608 rgb { 609 status = "disabled"; 610 }; 611 }; 612 613 dc@54240000 { 614 compatible = "nvidia,tegra20-dc"; 615 reg = <0x54240000 0x00040000>; 616 interrupts = <0 74 0x04>; 617 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 618 <&tegra_car TEGRA20_CLK_PLL_P>; 619 clock-names = "dc", "parent"; 620 resets = <&tegra_car 26>; 621 reset-names = "dc"; 622 operating-points-v2 = <&dvfs_opp_table>; 623 power-domains = <&domain>; 624 625 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, 626 <&mc TEGRA20_MC_DISPLAY0BB &emc>, 627 <&mc TEGRA20_MC_DISPLAY0CB &emc>, 628 <&mc TEGRA20_MC_DISPLAYHCB &emc>; 629 interconnect-names = "wina", 630 "winb", 631 "winc", 632 "cursor"; 633 634 rgb { 635 status = "disabled"; 636 }; 637 }; 638 639 hdmi { 640 compatible = "nvidia,tegra20-hdmi"; 641 reg = <0x54280000 0x00040000>; 642 interrupts = <0 75 0x04>; 643 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 644 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 645 clock-names = "hdmi", "parent"; 646 resets = <&tegra_car 51>; 647 reset-names = "hdmi"; 648 status = "disabled"; 649 operating-points-v2 = <&dvfs_opp_table>; 650 }; 651 652 tvo { 653 compatible = "nvidia,tegra20-tvo"; 654 reg = <0x542c0000 0x00040000>; 655 interrupts = <0 76 0x04>; 656 clocks = <&tegra_car TEGRA20_CLK_TVO>; 657 status = "disabled"; 658 operating-points-v2 = <&dvfs_opp_table>; 659 }; 660 661 dsi { 662 compatible = "nvidia,tegra20-dsi"; 663 reg = <0x54300000 0x00040000>; 664 clocks = <&tegra_car TEGRA20_CLK_DSI>, 665 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 666 clock-names = "dsi", "parent"; 667 resets = <&tegra_car 48>; 668 reset-names = "dsi"; 669 status = "disabled"; 670 operating-points-v2 = <&dvfs_opp_table>; 671 }; 672 }; 673 674 ... 675 };
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