fsl-qdma.txt

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    1 NXP Layerscape SoC qDMA Controller
    2 ==================================
    3 
    4 This device follows the generic DMA bindings defined in dma/dma.txt.
    5 
    6 Required properties:
    7 
    8 - compatible:           Must be one of
    9                          "fsl,ls1021a-qdma": for LS1021A Board
   10                          "fsl,ls1028a-qdma": for LS1028A Board
   11                          "fsl,ls1043a-qdma": for ls1043A Board
   12                          "fsl,ls1046a-qdma": for ls1046A Board
   13 - reg:                  Should contain the register's base address and length.
   14 - interrupts:           Should contain a reference to the interrupt used by this
   15                         device.
   16 - interrupt-names:      Should contain interrupt names:
   17                          "qdma-queue0": the block0 interrupt
   18                          "qdma-queue1": the block1 interrupt
   19                          "qdma-queue2": the block2 interrupt
   20                          "qdma-queue3": the block3 interrupt
   21                          "qdma-error":  the error interrupt
   22 - fsl,dma-queues:       Should contain number of queues supported.
   23 - dma-channels: Number of DMA channels supported
   24 - block-number: the virtual block number
   25 - block-offset: the offset of different virtual block
   26 - status-sizes: status queue size of per virtual block
   27 - queue-sizes:          command queue size of per virtual block, the size number
   28                         based on queues
   29 
   30 Optional properties:
   31 
   32 - dma-channels:         Number of DMA channels supported by the controller.
   33 - big-endian:           If present registers and hardware scatter/gather descriptors
   34                         of the qDMA are implemented in big endian mode, otherwise in little
   35                         mode.
   36 
   37 Examples:
   38 
   39         qdma: dma-controller@8390000 {
   40                         compatible = "fsl,ls1021a-qdma";
   41                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
   42                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
   43                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
   44                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
   45                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
   46                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
   47                         interrupt-names = "qdma-error",
   48                                 "qdma-queue0", "qdma-queue1";
   49                         dma-channels = <8>;
   50                         block-number = <2>;
   51                         block-offset = <0x1000>;
   52                         fsl,dma-queues = <2>;
   53                         status-sizes = <64>;
   54                         queue-sizes = <64 64>;
   55                         big-endian;
   56                 };
   57 
   58 DMA clients must use the format described in dma/dma.txt file.

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sys/contrib/device-tree/Bindings/dma/fsl-qdma.txt