snps,dma-spear1340.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Synopsys Designware DMA Controller
    8 
    9 maintainers:
   10   - Viresh Kumar <vireshk@kernel.org>
   11   - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   12 
   13 allOf:
   14   - $ref: "dma-controller.yaml#"
   15 
   16 properties:
   17   compatible:
   18     oneOf:
   19       - const: snps,dma-spear1340
   20       - items:
   21           - enum:
   22               - renesas,r9a06g032-dma
   23           - const: renesas,rzn1-dma
   24 
   25 
   26   "#dma-cells":
   27     minimum: 3
   28     maximum: 4
   29     description: |
   30       First cell is a phandle pointing to the DMA controller. Second one is
   31       the DMA request line number. Third cell is the memory master identifier
   32       for transfers on dynamically allocated channel. Fourth cell is the
   33       peripheral master identifier for transfers on an allocated channel. Fifth
   34       cell is an optional mask of the DMA channels permitted to be allocated
   35       for the corresponding client device.
   36 
   37   reg:
   38     maxItems: 1
   39 
   40   interrupts:
   41     maxItems: 1
   42 
   43   clocks:
   44     maxItems: 1
   45 
   46   clock-names:
   47     description: AHB interface reference clock.
   48     const: hclk
   49 
   50   dma-channels:
   51     description: |
   52       Number of DMA channels supported by the controller. In case if
   53       not specified the driver will try to auto-detect this and
   54       the rest of the optional parameters.
   55     minimum: 1
   56     maximum: 8
   57 
   58   dma-requests:
   59     minimum: 1
   60     maximum: 16
   61 
   62   dma-masters:
   63     $ref: /schemas/types.yaml#/definitions/uint32
   64     description: |
   65       Number of DMA masters supported by the controller. In case if
   66       not specified the driver will try to auto-detect this and
   67       the rest of the optional parameters.
   68     minimum: 1
   69     maximum: 4
   70 
   71   chan_allocation_order:
   72     $ref: /schemas/types.yaml#/definitions/uint32
   73     description: |
   74       DMA channels allocation order specifier. Zero means ascending order
   75       (first free allocated), while one - descending (last free allocated).
   76     default: 0
   77     enum: [0, 1]
   78 
   79   chan_priority:
   80     $ref: /schemas/types.yaml#/definitions/uint32
   81     description: |
   82       DMA channels priority order. Zero means ascending channels priority
   83       so the very first channel has the highest priority. While 1 means
   84       descending priority (the last channel has the highest priority).
   85     default: 0
   86     enum: [0, 1]
   87 
   88   block_size:
   89     $ref: /schemas/types.yaml#/definitions/uint32
   90     description: Maximum block size supported by the DMA controller.
   91     enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
   92 
   93   data-width:
   94     $ref: /schemas/types.yaml#/definitions/uint32-array
   95     description: Data bus width per each DMA master in bytes.
   96     items:
   97       maxItems: 4
   98       items:
   99         enum: [4, 8, 16, 32]
  100 
  101   data_width:
  102     $ref: /schemas/types.yaml#/definitions/uint32-array
  103     deprecated: true
  104     description: |
  105       Data bus width per each DMA master in (2^n * 8) bits. This property is
  106       deprecated. It' usage is discouraged in favor of data-width one. Moreover
  107       the property incorrectly permits to define data-bus width of 8 and 16
  108       bits, which is impossible in accordance with DW DMAC IP-core data book.
  109     items:
  110       maxItems: 4
  111       items:
  112         enum:
  113           - 0 # 8 bits
  114           - 1 # 16 bits
  115           - 2 # 32 bits
  116           - 3 # 64 bits
  117           - 4 # 128 bits
  118           - 5 # 256 bits
  119         default: 0
  120 
  121   multi-block:
  122     $ref: /schemas/types.yaml#/definitions/uint32-array
  123     description: |
  124       LLP-based multi-block transfer supported by hardware per
  125       each DMA channel.
  126     items:
  127       maxItems: 8
  128       items:
  129         enum: [0, 1]
  130         default: 1
  131 
  132   snps,max-burst-len:
  133     $ref: /schemas/types.yaml#/definitions/uint32-array
  134     description: |
  135       Maximum length of the burst transactions supported by the controller.
  136       This property defines the upper limit of the run-time burst setting
  137       (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
  138       will be from 1 to max-burst-len words. It's an array property with one
  139       cell per channel in the units determined by the value set in the
  140       CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
  141     items:
  142       maxItems: 8
  143       items:
  144         enum: [4, 8, 16, 32, 64, 128, 256]
  145         default: 256
  146 
  147   snps,dma-protection-control:
  148     $ref: /schemas/types.yaml#/definitions/uint32
  149     description: |
  150       Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
  151       indicates the following features: bit 0 - privileged mode,
  152       bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
  153     default: 0
  154     minimum: 0
  155     maximum: 7
  156 
  157 unevaluatedProperties: false
  158 
  159 required:
  160   - compatible
  161   - "#dma-cells"
  162   - reg
  163   - interrupts
  164 
  165 examples:
  166   - |
  167     dma-controller@fc000000 {
  168       compatible = "snps,dma-spear1340";
  169       reg = <0xfc000000 0x1000>;
  170       interrupt-parent = <&vic1>;
  171       interrupts = <12>;
  172 
  173       dma-channels = <8>;
  174       dma-requests = <16>;
  175       dma-masters = <4>;
  176       #dma-cells = <3>;
  177 
  178       chan_allocation_order = <1>;
  179       chan_priority = <1>;
  180       block_size = <0xfff>;
  181       data-width = <8 8>;
  182       multi-block = <0 0 0 0 0 0 0 0>;
  183       snps,max-burst-len = <16 16 4 4 4 4 4 4>;
  184     };
  185 ...

Cache object: 73e0b1f8f2d7d36cd67436137d50d171

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sys/contrib/device-tree/Bindings/dma/snps,dma-spear1340.yaml