The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/dma/snps,dw-axi-dmac.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Synopsys DesignWare AXI DMA Controller
    8 
    9 maintainers:
   10   - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   11   - Jee Heng Sia <jee.heng.sia@intel.com>
   12 
   13 description:
   14   Synopsys DesignWare AXI DMA Controller DT Binding
   15 
   16 allOf:
   17   - $ref: "dma-controller.yaml#"
   18 
   19 properties:
   20   compatible:
   21     enum:
   22       - snps,axi-dma-1.01a
   23       - intel,kmb-axi-dma
   24 
   25   reg:
   26     minItems: 1
   27     items:
   28       - description: Address range of the DMAC registers
   29       - description: Address range of the DMAC APB registers
   30 
   31   reg-names:
   32     items:
   33       - const: axidma_ctrl_regs
   34       - const: axidma_apb_regs
   35 
   36   interrupts:
   37     description:
   38       If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
   39       will be per-channel interrupts. Otherwise, this is a single combined IRQ
   40       for all channels.
   41     minItems: 1
   42     maxItems: 8
   43 
   44   clocks:
   45     items:
   46       - description: Bus Clock
   47       - description: Module Clock
   48 
   49   clock-names:
   50     items:
   51       - const: core-clk
   52       - const: cfgr-clk
   53 
   54   '#dma-cells':
   55     const: 1
   56 
   57   dma-channels:
   58     minimum: 1
   59     maximum: 8
   60 
   61   resets:
   62     maxItems: 1
   63 
   64   snps,dma-masters:
   65     description: |
   66       Number of AXI masters supported by the hardware.
   67     $ref: /schemas/types.yaml#/definitions/uint32
   68     enum: [1, 2]
   69 
   70   snps,data-width:
   71     description: |
   72       AXI data width supported by hardware.
   73       (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
   74     $ref: /schemas/types.yaml#/definitions/uint32
   75     enum: [0, 1, 2, 3, 4, 5, 6]
   76 
   77   snps,priority:
   78     description: |
   79       Channel priority specifier associated with the DMA channels.
   80     $ref: /schemas/types.yaml#/definitions/uint32-array
   81     minItems: 1
   82     maxItems: 8
   83 
   84   snps,block-size:
   85     description: |
   86       Channel block size specifier associated with the DMA channels.
   87     $ref: /schemas/types.yaml#/definitions/uint32-array
   88     minItems: 1
   89     maxItems: 8
   90 
   91   snps,axi-max-burst-len:
   92     description: |
   93       Restrict master AXI burst length by value specified in this property.
   94       If this property is missing the maximum AXI burst length supported by
   95       DMAC is used.
   96     $ref: /schemas/types.yaml#/definitions/uint32
   97     minimum: 1
   98     maximum: 256
   99 
  100 required:
  101   - compatible
  102   - reg
  103   - clocks
  104   - clock-names
  105   - interrupts
  106   - '#dma-cells'
  107   - dma-channels
  108   - snps,dma-masters
  109   - snps,data-width
  110   - snps,priority
  111   - snps,block-size
  112 
  113 additionalProperties: false
  114 
  115 examples:
  116   - |
  117      #include <dt-bindings/interrupt-controller/arm-gic.h>
  118      #include <dt-bindings/interrupt-controller/irq.h>
  119      /* example with snps,dw-axi-dmac */
  120      dmac: dma-controller@80000 {
  121          compatible = "snps,axi-dma-1.01a";
  122          reg = <0x80000 0x400>;
  123          clocks = <&core_clk>, <&cfgr_clk>;
  124          clock-names = "core-clk", "cfgr-clk";
  125          interrupt-parent = <&intc>;
  126          interrupts = <27>;
  127          #dma-cells = <1>;
  128          dma-channels = <4>;
  129          snps,dma-masters = <2>;
  130          snps,data-width = <3>;
  131          snps,block-size = <4096 4096 4096 4096>;
  132          snps,priority = <0 1 2 3>;
  133          snps,axi-max-burst-len = <16>;
  134      };

Cache object: 7564fcf39451b0b8ccc8e62a1dacacde


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