1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated
3 # Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
4 %YAML 1.2
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
8
9 title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings
10
11 maintainers:
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
13
14 description: |
15 The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
16 mode channels of K3 UDMA-P.
17 PKTDMA only includes Split channels to service PSI-L based peripherals.
18
19 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
20 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
21 legacy peripheral.
22
23 PDMAs can be configured via PKTDMA split channel's peer registers to match
24 with the configuration of the legacy peripheral.
25
26 allOf:
27 - $ref: /schemas/dma/dma-controller.yaml#
28 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
29
30 properties:
31 compatible:
32 const: ti,am64-dmss-pktdma
33
34 "#dma-cells":
35 const: 2
36 description: |
37 The first cell is the PSI-L thread ID of the remote (to PKTDMA) end.
38 Valid ranges for thread ID depends on the data movement direction:
39 for source thread IDs (rx): 0 - 0x7fff
40 for destination thread IDs (tx): 0x8000 - 0xffff
41
42 Please refer to the device documentation for the PSI-L thread map and also
43 the PSI-L peripheral chapter for the correct thread ID.
44
45 The second cell is the ASEL value for the channel
46
47 reg:
48 maxItems: 4
49
50 reg-names:
51 items:
52 - const: gcfg
53 - const: rchanrt
54 - const: tchanrt
55 - const: ringrt
56
57 msi-parent: true
58
59 ti,sci-rm-range-tchan:
60 $ref: /schemas/types.yaml#/definitions/uint32-array
61 description: |
62 Array of PKTDMA split tx channel resource subtypes for resource allocation
63 for this host
64 minItems: 1
65 # Should be enough
66 maxItems: 255
67 items:
68 maximum: 0x3f
69
70 ti,sci-rm-range-tflow:
71 $ref: /schemas/types.yaml#/definitions/uint32-array
72 description: |
73 Array of PKTDMA split tx flow resource subtypes for resource allocation
74 for this host
75 minItems: 1
76 # Should be enough
77 maxItems: 255
78 items:
79 maximum: 0x3f
80
81 ti,sci-rm-range-rchan:
82 $ref: /schemas/types.yaml#/definitions/uint32-array
83 description: |
84 Array of PKTDMA split rx channel resource subtypes for resource allocation
85 for this host
86 minItems: 1
87 # Should be enough
88 maxItems: 255
89 items:
90 maximum: 0x3f
91
92 ti,sci-rm-range-rflow:
93 $ref: /schemas/types.yaml#/definitions/uint32-array
94 description: |
95 Array of PKTDMA split rx flow resource subtypes for resource allocation
96 for this host
97 minItems: 1
98 # Should be enough
99 maxItems: 255
100 items:
101 maximum: 0x3f
102
103 required:
104 - compatible
105 - "#dma-cells"
106 - reg
107 - reg-names
108 - msi-parent
109 - ti,sci
110 - ti,sci-dev-id
111 - ti,sci-rm-range-tchan
112 - ti,sci-rm-range-tflow
113 - ti,sci-rm-range-rchan
114 - ti,sci-rm-range-rflow
115
116 unevaluatedProperties: false
117
118 examples:
119 - |+
120 cbass_main {
121 #address-cells = <2>;
122 #size-cells = <2>;
123
124 main_dmss {
125 compatible = "simple-mfd";
126 #address-cells = <2>;
127 #size-cells = <2>;
128 dma-ranges;
129 ranges;
130
131 ti,sci-dev-id = <25>;
132
133 main_pktdma: dma-controller@485c0000 {
134 compatible = "ti,am64-dmss-pktdma";
135
136 reg = <0x0 0x485c0000 0x0 0x100>,
137 <0x0 0x4a800000 0x0 0x20000>,
138 <0x0 0x4aa00000 0x0 0x40000>,
139 <0x0 0x4b800000 0x0 0x400000>;
140 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
141 msi-parent = <&inta_main_dmss>;
142 #dma-cells = <2>;
143
144 ti,sci = <&dmsc>;
145 ti,sci-dev-id = <30>;
146
147 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
148 <0x24>, /* CPSW_TX_CHAN */
149 <0x25>, /* SAUL_TX_0_CHAN */
150 <0x26>, /* SAUL_TX_1_CHAN */
151 <0x27>, /* ICSSG_0_TX_CHAN */
152 <0x28>; /* ICSSG_1_TX_CHAN */
153 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
154 <0x11>, /* RING_CPSW_TX_CHAN */
155 <0x12>, /* RING_SAUL_TX_0_CHAN */
156 <0x13>, /* RING_SAUL_TX_1_CHAN */
157 <0x14>, /* RING_ICSSG_0_TX_CHAN */
158 <0x15>; /* RING_ICSSG_1_TX_CHAN */
159 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
160 <0x2b>, /* CPSW_RX_CHAN */
161 <0x2d>, /* SAUL_RX_0_CHAN */
162 <0x2f>, /* SAUL_RX_1_CHAN */
163 <0x31>, /* SAUL_RX_2_CHAN */
164 <0x33>, /* SAUL_RX_3_CHAN */
165 <0x35>, /* ICSSG_0_RX_CHAN */
166 <0x37>; /* ICSSG_1_RX_CHAN */
167 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
168 <0x2c>, /* FLOW_CPSW_RX_CHAN */
169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
171 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
172 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
173 };
174 };
175 };
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