1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: NXP i.MX8 DSP core
8
9 maintainers:
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
12
13 description: |
14 Some boards from i.MX8 family contain a DSP core used for
15 advanced pre- and post- audio processing.
16
17 properties:
18 compatible:
19 enum:
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8qxp-hifi4
24 - fsl,imx8qm-hifi4
25 - fsl,imx8mp-hifi4
26 - fsl,imx8ulp-hifi4
27
28 reg:
29 maxItems: 1
30
31 clocks:
32 items:
33 - description: ipg clock
34 - description: ocram clock
35 - description: core clock
36 - description: debug interface clock
37 - description: message unit clock
38 minItems: 3
39
40 clock-names:
41 items:
42 - const: ipg
43 - const: ocram
44 - const: core
45 - const: debug
46 - const: mu
47 minItems: 3
48
49 power-domains:
50 description:
51 List of phandle and PM domain specifier as documented in
52 Documentation/devicetree/bindings/power/power_domain.txt
53 minItems: 1
54 maxItems: 4
55
56 mboxes:
57 description:
58 List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
59 or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
60 (see mailbox/fsl,mu.txt)
61 minItems: 3
62 maxItems: 4
63
64 mbox-names:
65 minItems: 3
66 maxItems: 4
67
68 memory-region:
69 description:
70 phandle to a node describing reserved memory (System RAM memory)
71 used by DSP (see bindings/reserved-memory/reserved-memory.txt)
72 minItems: 1
73 maxItems: 4
74
75 firmware-name:
76 description: |
77 Default name of the firmware to load to the remote processor.
78
79 fsl,dsp-ctrl:
80 $ref: /schemas/types.yaml#/definitions/phandle
81 description:
82 Phandle to syscon block which provide access for processor enablement
83
84 required:
85 - compatible
86 - reg
87 - clocks
88 - clock-names
89 - power-domains
90 - mboxes
91 - mbox-names
92 - memory-region
93
94 allOf:
95 - if:
96 properties:
97 compatible:
98 contains:
99 enum:
100 - fsl,imx8qxp-dsp
101 - fsl,imx8qm-dsp
102 - fsl,imx8qxp-hifi4
103 - fsl,imx8qm-hifi4
104 then:
105 properties:
106 power-domains:
107 minItems: 4
108 else:
109 properties:
110 power-domains:
111 maxItems: 1
112
113 - if:
114 properties:
115 compatible:
116 contains:
117 enum:
118 - fsl,imx8qxp-hifi4
119 - fsl,imx8qm-hifi4
120 - fsl,imx8mp-hifi4
121 - fsl,imx8ulp-hifi4
122 then:
123 properties:
124 memory-region:
125 minItems: 4
126 mboxes:
127 maxItems: 3
128 mbox-names:
129 items:
130 - const: tx
131 - const: rx
132 - const: rxdb
133 else:
134 properties:
135 memory-region:
136 maxItems: 1
137 mboxes:
138 minItems: 4
139 mbox-names:
140 items:
141 - const: txdb0
142 - const: txdb1
143 - const: rxdb0
144 - const: rxdb1
145
146 additionalProperties: false
147
148 examples:
149 - |
150 #include <dt-bindings/firmware/imx/rsrc.h>
151 #include <dt-bindings/clock/imx8-clock.h>
152 dsp@596e8000 {
153 compatible = "fsl,imx8qxp-dsp";
154 reg = <0x596e8000 0x88000>;
155 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
156 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
157 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
158 clock-names = "ipg", "ocram", "core";
159 power-domains = <&pd IMX_SC_R_MU_13A>,
160 <&pd IMX_SC_R_MU_13B>,
161 <&pd IMX_SC_R_DSP>,
162 <&pd IMX_SC_R_DSP_RAM>;
163 mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
164 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
165 memory-region = <&dsp_reserved>;
166 };
167 - |
168 #include <dt-bindings/clock/imx8mp-clock.h>
169 dsp_reserved: dsp@92400000 {
170 reg = <0x92400000 0x1000000>;
171 no-map;
172 };
173 dsp_vdev0vring0: vdev0vring0@942f0000 {
174 reg = <0x942f0000 0x8000>;
175 no-map;
176 };
177 dsp_vdev0vring1: vdev0vring1@942f8000 {
178 reg = <0x942f8000 0x8000>;
179 no-map;
180 };
181 dsp_vdev0buffer: vdev0buffer@94300000 {
182 compatible = "shared-dma-pool";
183 reg = <0x94300000 0x100000>;
184 no-map;
185 };
186
187 dsp: dsp@3b6e8000 {
188 compatible = "fsl,imx8mp-hifi4";
189 reg = <0x3b6e8000 0x88000>;
190 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
191 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
192 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
193 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
194 clock-names = "ipg", "ocram", "core", "debug";
195 firmware-name = "imx/dsp/hifi4.bin";
196 power-domains = <&audiomix_pd>;
197 mbox-names = "tx", "rx", "rxdb";
198 mboxes = <&mu2 0 0>,
199 <&mu2 1 0>,
200 <&mu2 3 0>;
201 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
202 <&dsp_vdev0vring1>, <&dsp_reserved>;
203 fsl,dsp-ctrl = <&audio_blk_ctrl>;
204 };
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