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     1 EEPROMs (SPI) compatible with Atmel at25.
    2 
    3 Required properties:
    4 - compatible : Should be "<vendor>,<type>", and generic value "atmel,at25".
    5   Example "<vendor>,<type>" values:
    6     "anvo,anv32e61w"
    7     "microchip,25lc040"
    8     "st,m95m02"
    9     "st,m95256"
   10 
   11 - reg : chip select number
   12 - spi-max-frequency : max spi frequency to use
   13 - pagesize : size of the eeprom page
   14 - size : total eeprom size in bytes
   15 - address-width : number of address bits (one of 8, 9, 16, or 24).
   16   For 9 bits, the MSB of the address is sent as bit 3 of the instruction
   17   byte, before the address byte.
   18 
   19 Optional properties:
   20 - spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
   21 - spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
   22 - read-only : this parameter-less property disables writes to the eeprom
   23 - wp-gpios : GPIO to which the write-protect pin of the chip is connected
   24 
   25 Obsolete legacy properties can be used in place of "size", "pagesize",
   26 "address-width", and "read-only":
   27 - at25,byte-len : total eeprom size in bytes
   28 - at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h
   29 - at25,page-size : size of the eeprom page
   30 
   31 Additional compatible properties are also allowed.
   32 
   33 Example:
   34         eeprom@0 {
   35                 compatible = "st,m95256", "atmel,at25";
   36                 reg = <0>
   37                 spi-max-frequency = <5000000>;
   38                 spi-cpha;
   39                 spi-cpol;
   40                 wp-gpios = <&gpio1 3 0>;
   41 
   42                 pagesize = <64>;
   43                 size = <32768>;
   44                 address-width = <16>;
   45         };
Cache object: 9aa91c2518d76fcb42e89aff1483546b 
 
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