The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Xilinx firmware driver
    8 
    9 maintainers:
   10   - Nava kishore Manne <nava.manne@xilinx.com>
   11 
   12 description: The zynqmp-firmware node describes the interface to platform
   13   firmware. ZynqMP has an interface to communicate with secure firmware.
   14   Firmware driver provides an interface to firmware APIs. Interface APIs
   15   can be used by any driver to communicate to PMUFW(Platform Management Unit).
   16   These requests include clock management, pin control, device control,
   17   power management service, FPGA service and other platform management
   18   services.
   19 
   20 properties:
   21   compatible:
   22     oneOf:
   23       - description: For implementations complying for Zynq Ultrascale+ MPSoC.
   24         const: xlnx,zynqmp-firmware
   25 
   26       - description: For implementations complying for Versal.
   27         const: xlnx,versal-firmware
   28 
   29   method:
   30     description: |
   31                  The method of calling the PM-API firmware layer.
   32                  Permitted values are.
   33                  - "smc" : SMC #0, following the SMCCC
   34                  - "hvc" : HVC #0, following the SMCCC
   35 
   36     $ref: /schemas/types.yaml#/definitions/string-array
   37     enum:
   38       - smc
   39       - hvc
   40 
   41   versal_fpga:
   42     $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
   43     description: Compatible of the FPGA device.
   44     type: object
   45 
   46   zynqmp-aes:
   47     $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
   48     description: The ZynqMP AES-GCM hardened cryptographic accelerator is
   49       used to encrypt or decrypt the data with provided key and initialization
   50       vector.
   51     type: object
   52 
   53   clock-controller:
   54     $ref: /schemas/clock/xlnx,versal-clk.yaml#
   55     description: The clock controller is a hardware block of Xilinx versal
   56       clock tree. It reads required input clock frequencies from the devicetree
   57       and acts as clock provider for all clock consumers of PS clocks.list of
   58       clock specifiers which are external input clocks to the given clock
   59       controller.
   60     type: object
   61 
   62 required:
   63   - compatible
   64 
   65 additionalProperties: false
   66 
   67 examples:
   68   - |
   69     versal-firmware {
   70       compatible = "xlnx,versal-firmware";
   71       method = "smc";
   72 
   73       versal_fpga: versal_fpga {
   74         compatible = "xlnx,versal-fpga";
   75       };
   76 
   77       xlnx_aes: zynqmp-aes {
   78         compatible = "xlnx,zynqmp-aes";
   79       };
   80 
   81       versal_clk: clock-controller {
   82         #clock-cells = <1>;
   83         compatible = "xlnx,versal-clk";
   84         clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
   85         clock-names = "ref", "alt_ref", "pl_alt_ref";
   86       };
   87     };
   88 
   89 ...

Cache object: 7bd4152cb3807cd4be733a4272f780fc


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