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     1 Altera Passive Serial SPI FPGA Manager
    2 
    3 Altera FPGAs support a method of loading the bitstream over what is
    4 referred to as "passive serial".
    5 The passive serial link is not technically SPI, and might require extra
    6 circuits in order to play nicely with other SPI slaves on the same bus.
    7 
    8 See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
    9 
   10 Required properties:
   11 - compatible: Must be one of the following:
   12         "altr,fpga-passive-serial",
   13         "altr,fpga-arria10-passive-serial"
   14 - reg: SPI chip select of the FPGA
   15 - nconfig-gpios: config pin (referred to as nCONFIG in the manual)
   16 - nstat-gpios: status pin (referred to as nSTATUS in the manual)
   17 
   18 Optional properties:
   19 - confd-gpios: confd pin (referred to as CONF_DONE in the manual)
   20 
   21 Example:
   22         fpga: fpga@0 {
   23                 compatible = "altr,fpga-passive-serial";
   24                 spi-max-frequency = <20000000>;
   25                 reg = <0>;
   26                 nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
   27                 nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
   28                 confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
   29         };
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