brcm,brcmstb-gpio.txt

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    1 Broadcom STB "UPG GIO" GPIO controller
    2 
    3 The controller's registers are organized as sets of eight 32-bit
    4 registers with each set controlling a bank of up to 32 pins.  A single
    5 interrupt is shared for all of the banks handled by the controller.
    6 
    7 Required properties:
    8 
    9 - compatible:
   10     Must be "brcm,brcmstb-gpio"
   11 
   12 - reg:
   13     Define the base and range of the I/O address space containing
   14     the brcmstb GPIO controller registers
   15 
   16 - #gpio-cells:
   17     Should be <2>.  The first cell is the pin number (within the controller's
   18     pin space), and the second is used for the following:
   19     bit[0]: polarity (0 for active-high, 1 for active-low)
   20 
   21 - gpio-controller:
   22     Specifies that the node is a GPIO controller.
   23 
   24 - brcm,gpio-bank-widths:
   25     Number of GPIO lines for each bank.  Number of elements must
   26     correspond to number of banks suggested by the 'reg' property.
   27 
   28 Optional properties:
   29 
   30 - interrupts:
   31     The interrupt shared by all GPIO lines for this controller.
   32 
   33 - interrupts-extended:
   34     Alternate form of specifying interrupts and parents that allows for
   35     multiple parents.  This takes precedence over 'interrupts' and
   36     'interrupt-parent'.  Wakeup-capable GPIO controllers often route their
   37     wakeup interrupt lines through a different interrupt controller than the
   38     primary interrupt line, making this property necessary.
   39 
   40 - #interrupt-cells:
   41     Should be <2>.  The first cell is the GPIO number, the second should specify
   42     flags.  The following subset of flags is supported:
   43     - bits[3:0] trigger type and level flags
   44         1 = low-to-high edge triggered
   45         2 = high-to-low edge triggered
   46         4 = active high level-sensitive
   47         8 = active low level-sensitive
   48       Valid combinations are 1, 2, 3, 4, 8.
   49     See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
   50 
   51 - interrupt-controller:
   52     Marks the device node as an interrupt controller
   53 
   54 - wakeup-source:
   55     GPIOs for this controller can be used as a wakeup source
   56 
   57 Example:
   58         upg_gio: gpio@f040a700 {
   59                 #gpio-cells = <2>;
   60                 #interrupt-cells = <2>;
   61                 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
   62                 gpio-controller;
   63                 interrupt-controller;
   64                 reg = <0xf040a700 0x80>;
   65                 interrupt-parent = <&irq0_intc>;
   66                 interrupts = <0x6>;
   67                 brcm,gpio-bank-widths = <32 32 32 24>;
   68         };
   69 
   70         upg_gio_aon: gpio@f04172c0 {
   71                 #gpio-cells = <2>;
   72                 #interrupt-cells = <2>;
   73                 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
   74                 gpio-controller;
   75                 interrupt-controller;
   76                 reg = <0xf04172c0 0x40>;
   77                 interrupt-parent = <&irq0_aon_intc>;
   78                 interrupts = <0x6>;
   79                 interrupts-extended = <&irq0_aon_intc 0x6>,
   80                         <&aon_pm_l2_intc 0x5>;
   81                 wakeup-source;
   82                 brcm,gpio-bank-widths = <18 4>;
   83         };

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sys/contrib/device-tree/Bindings/gpio/brcm,brcmstb-gpio.txt