brcm,brcmstb-gpio.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Broadcom STB "UPG GIO" GPIO controller
    8 
    9 description: >
   10   The controller's registers are organized as sets of eight 32-bit
   11   registers with each set controlling a bank of up to 32 pins.  A single
   12   interrupt is shared for all of the banks handled by the controller.
   13 
   14 maintainers:
   15   - Doug Berger <opendmb@gmail.com>
   16   - Florian Fainelli <f.fainelli@gmail.com>
   17 
   18 properties:
   19   compatible:
   20     items:
   21       - enum:
   22           - brcm,bcm7445-gpio
   23       - const: brcm,brcmstb-gpio
   24 
   25   reg:
   26     maxItems: 1
   27     description: >
   28       Define the base and range of the I/O address space containing
   29       the brcmstb GPIO controller registers
   30 
   31   "#gpio-cells":
   32     const: 2
   33     description: >
   34       The first cell is the pin number (within the controller's
   35       pin space), and the second is used for the following:
   36       bit[0]: polarity (0 for active-high, 1 for active-low)
   37 
   38   gpio-controller: true
   39 
   40   brcm,gpio-bank-widths:
   41     $ref: /schemas/types.yaml#/definitions/uint32-array
   42     description: >
   43       Number of GPIO lines for each bank.  Number of elements must
   44       correspond to number of banks suggested by the 'reg' property.
   45 
   46   interrupts:
   47     maxItems: 1
   48     description: >
   49       The interrupt shared by all GPIO lines for this controller.
   50 
   51   "#interrupt-cells":
   52     const: 2
   53     description: |
   54       The first cell is the GPIO number, the second should specify
   55       flags.  The following subset of flags is supported:
   56       - bits[3:0] trigger type and level flags
   57         1 = low-to-high edge triggered
   58         2 = high-to-low edge triggered
   59         4 = active high level-sensitive
   60         8 = active low level-sensitive
   61       Valid combinations are 1, 2, 3, 4, 8.
   62 
   63   interrupt-controller: true
   64 
   65   wakeup-source:
   66     type: boolean
   67     description: >
   68       GPIOs for this controller can be used as a wakeup source
   69 
   70 required:
   71   - compatible
   72   - reg
   73   - gpio-controller
   74   - "#gpio-cells"
   75   - "brcm,gpio-bank-widths"
   76 
   77 additionalProperties: false
   78 
   79 examples:
   80   - |
   81     upg_gio: gpio@f040a700 {
   82         #gpio-cells = <2>;
   83         #interrupt-cells = <2>;
   84         compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
   85         gpio-controller;
   86         interrupt-controller;
   87         reg = <0xf040a700 0x80>;
   88         interrupt-parent = <&irq0_intc>;
   89         interrupts = <0x6>;
   90         brcm,gpio-bank-widths = <32 32 32 24>;
   91     };
   92 
   93     upg_gio_aon: gpio@f04172c0 {
   94         #gpio-cells = <2>;
   95         #interrupt-cells = <2>;
   96         compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
   97         gpio-controller;
   98         interrupt-controller;
   99         reg = <0xf04172c0 0x40>;
  100         interrupt-parent = <&irq0_aon_intc>;
  101         interrupts = <0x6>;
  102         wakeup-source;
  103         brcm,gpio-bank-widths = <18 4>;
  104     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/gpio/brcm,brcmstb-gpio.yaml

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sys/contrib/device-tree/Bindings/gpio/brcm,brcmstb-gpio.yaml