The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
    5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
    6 
    7 title: Device tree binding for NVIDIA Tegra NVENC
    8 
    9 description: |
   10   NVENC is the hardware video encoder present on NVIDIA Tegra210
   11   and newer chips. It is located on the Host1x bus and typically
   12   programmed through Host1x channels.
   13 
   14 maintainers:
   15   - Thierry Reding <treding@gmail.com>
   16   - Mikko Perttunen <mperttunen@nvidia.com>
   17 
   18 properties:
   19   $nodename:
   20     pattern: "^nvenc@[0-9a-f]*$"
   21 
   22   compatible:
   23     enum:
   24       - nvidia,tegra210-nvenc
   25       - nvidia,tegra186-nvenc
   26       - nvidia,tegra194-nvenc
   27 
   28   reg:
   29     maxItems: 1
   30 
   31   clocks:
   32     maxItems: 1
   33 
   34   clock-names:
   35     items:
   36       - const: nvenc
   37 
   38   resets:
   39     maxItems: 1
   40 
   41   reset-names:
   42     items:
   43       - const: nvenc
   44 
   45   power-domains:
   46     maxItems: 1
   47 
   48   iommus:
   49     maxItems: 1
   50 
   51   dma-coherent: true
   52 
   53   interconnects:
   54     minItems: 2
   55     maxItems: 3
   56 
   57   interconnect-names:
   58     minItems: 2
   59     maxItems: 3
   60 
   61   nvidia,host1x-class:
   62     description: |
   63       Host1x class of the engine, used to specify the targeted engine
   64       when programming the engine through Host1x channels or when
   65       configuring engine-specific behavior in Host1x.
   66     default: 0x21
   67     $ref: /schemas/types.yaml#/definitions/uint32
   68 
   69 required:
   70   - compatible
   71   - reg
   72   - clocks
   73   - clock-names
   74   - resets
   75   - reset-names
   76   - power-domains
   77 
   78 allOf:
   79   - if:
   80       properties:
   81         compatible:
   82           enum:
   83             - nvidia,tegra210-nvenc
   84             - nvidia,tegra186-nvenc
   85     then:
   86       properties:
   87         interconnects:
   88           items:
   89             - description: DMA read memory client
   90             - description: DMA write memory client
   91         interconnect-names:
   92           items:
   93             - const: dma-mem
   94             - const: write
   95   - if:
   96       properties:
   97         compatible:
   98           enum:
   99             - nvidia,tegra194-nvenc
  100     then:
  101       properties:
  102         interconnects:
  103           items:
  104             - description: DMA read memory client
  105             - description: DMA read 2 memory client
  106             - description: DMA write memory client
  107         interconnect-names:
  108           items:
  109             - const: dma-mem
  110             - const: read-1
  111             - const: write
  112 
  113 additionalProperties: false
  114 
  115 examples:
  116   - |
  117     #include <dt-bindings/clock/tegra186-clock.h>
  118     #include <dt-bindings/memory/tegra186-mc.h>
  119     #include <dt-bindings/power/tegra186-powergate.h>
  120     #include <dt-bindings/reset/tegra186-reset.h>
  121 
  122     nvenc@154c0000 {
  123             compatible = "nvidia,tegra186-nvenc";
  124             reg = <0x154c0000 0x40000>;
  125             clocks = <&bpmp TEGRA186_CLK_NVENC>;
  126             clock-names = "nvenc";
  127             resets = <&bpmp TEGRA186_RESET_NVENC>;
  128             reset-names = "nvenc";
  129 
  130             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
  131             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
  132                             <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
  133             interconnect-names = "dma-mem", "write";
  134             iommus = <&smmu TEGRA186_SID_NVENC>;
  135     };

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