The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
    5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
    6 
    7 title: Device tree binding for NVIDIA Tegra NVJPG
    8 
    9 description: |
   10   NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
   11   and newer chips. It is located on the Host1x bus and typically programmed
   12   through Host1x channels.
   13 
   14 maintainers:
   15   - Thierry Reding <treding@gmail.com>
   16   - Mikko Perttunen <mperttunen@nvidia.com>
   17 
   18 properties:
   19   $nodename:
   20     pattern: "^nvjpg@[0-9a-f]*$"
   21 
   22   compatible:
   23     enum:
   24       - nvidia,tegra210-nvjpg
   25       - nvidia,tegra186-nvjpg
   26       - nvidia,tegra194-nvjpg
   27 
   28   reg:
   29     maxItems: 1
   30 
   31   clocks:
   32     maxItems: 1
   33 
   34   clock-names:
   35     items:
   36       - const: nvjpg
   37 
   38   resets:
   39     maxItems: 1
   40 
   41   reset-names:
   42     items:
   43       - const: nvjpg
   44 
   45   power-domains:
   46     maxItems: 1
   47 
   48   iommus:
   49     maxItems: 1
   50 
   51   dma-coherent: true
   52 
   53   interconnects:
   54     items:
   55       - description: DMA read memory client
   56       - description: DMA write memory client
   57 
   58   interconnect-names:
   59     items:
   60       - const: dma-mem
   61       - const: write
   62 
   63 required:
   64   - compatible
   65   - reg
   66   - clocks
   67   - clock-names
   68   - resets
   69   - reset-names
   70   - power-domains
   71 
   72 additionalProperties: false
   73 
   74 examples:
   75   - |
   76     #include <dt-bindings/clock/tegra186-clock.h>
   77     #include <dt-bindings/memory/tegra186-mc.h>
   78     #include <dt-bindings/power/tegra186-powergate.h>
   79     #include <dt-bindings/reset/tegra186-reset.h>
   80 
   81     nvjpg@15380000 {
   82             compatible = "nvidia,tegra186-nvjpg";
   83             reg = <0x15380000 0x40000>;
   84             clocks = <&bpmp TEGRA186_CLK_NVJPG>;
   85             clock-names = "nvjpg";
   86             resets = <&bpmp TEGRA186_RESET_NVJPG>;
   87             reset-names = "nvjpg";
   88 
   89             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
   90             interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
   91                             <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
   92             interconnect-names = "dma-mem", "write";
   93             iommus = <&smmu TEGRA186_SID_NVJPG>;
   94     };

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