1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Analog Devices AXI ADC IP core
8
9 maintainers:
10 - Michael Hennerich <michael.hennerich@analog.com>
11
12 description: |
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
14 with a high speed serial (JESD204B/C) or source synchronous parallel
15 interface (LVDS/CMOS).
16 Usually, some other interface type (i.e SPI) is used as a control
17 interface for the actual ADC, while this IP core will interface
18 to the data-lines of the ADC and handle the streaming of data into
19 memory via DMA.
20
21 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
22
23 properties:
24 compatible:
25 enum:
26 - adi,axi-adc-10.0.a
27
28 reg:
29 maxItems: 1
30
31 dmas:
32 maxItems: 1
33
34 dma-names:
35 items:
36 - const: rx
37
38 adi,adc-dev:
39 $ref: /schemas/types.yaml#/definitions/phandle
40 description:
41 A reference to a the actual ADC to which this FPGA ADC interfaces to.
42
43 required:
44 - compatible
45 - dmas
46 - reg
47 - adi,adc-dev
48
49 additionalProperties: false
50
51 examples:
52 - |
53 axi-adc@44a00000 {
54 compatible = "adi,axi-adc-10.0.a";
55 reg = <0x44a00000 0x10000>;
56 dmas = <&rx_dma 0>;
57 dma-names = "rx";
58
59 adi,adc-dev = <&spi_adc>;
60 };
61 ...
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