The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/iio/dac/ad5755.txt

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 * Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
    2 
    3 Required properties:
    4  - compatible: Has to contain one of the following:
    5         adi,ad5755
    6         adi,ad5755-1
    7         adi,ad5757
    8         adi,ad5735
    9         adi,ad5737
   10 
   11  - reg: spi chip select number for the device
   12  - spi-cpha or spi-cpol: is the only modes that is supported
   13 
   14 Recommended properties:
   15  - spi-max-frequency: Definition as per
   16                 Documentation/devicetree/bindings/spi/spi-bus.txt
   17 
   18 Optional properties:
   19 See include/dt-bindings/iio/ad5755.h
   20  - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
   21                                          external resistor and thereby bypasses
   22                                          the internal compensation resistor.
   23  - adi,dc-dc-phase:
   24         Valid values for DC DC Phase control is:
   25         0: All dc-to-dc converters clock on the same edge.
   26         1: Channel A and Channel B clock on the same edge,
   27            Channel C and Channel D clock on opposite edges.
   28         2: Channel A and Channel C clock on the same edge,
   29            Channel B and Channel D clock on opposite edges.
   30         3: Channel A, Channel B, Channel C, and Channel D
   31            clock 90 degrees out of phase from each other.
   32  - adi,dc-dc-freq-hz:
   33         Valid values for DC DC frequency is [Hz]:
   34         250000
   35         410000
   36         650000
   37  - adi,dc-dc-max-microvolt:
   38         Valid values for the maximum allowed Vboost voltage supplied by
   39         the dc-to-dc converter is:
   40         23000000
   41         24500000
   42         27000000
   43         29500000
   44 
   45 Optional for every channel:
   46  - adi,mode:
   47         Valid values for DAC modes is:
   48         0: 0 V to 5 V voltage range.
   49         1: 0 V to 10 V voltage range.
   50         2: Plus minus 5 V voltage range.
   51         3: Plus minus 10 V voltage range.
   52         4: 4 mA to 20 mA current range.
   53         5: 0 mA to 20 mA current range.
   54         6: 0 mA to 24 mA current range.
   55  - adi,ext-current-sense-resistor: boolean set if the hardware a external
   56                                    current sense resistor.
   57  - adi,enable-voltage-overrange: boolean enable voltage overrange
   58  - adi,slew: Array of slewrate settings should contain 3 fields:
   59         1: Should be either 0 or 1 in order to enable or disable slewrate.
   60         2: Slew rate settings:
   61                 Valid values for the slew rate update frequency:
   62                 64000
   63                 32000
   64                 16000
   65                 8000
   66                 4000
   67                 2000
   68                 1000
   69                 500
   70                 250
   71                 125
   72                 64
   73                 32
   74                 16
   75                 8
   76                 4
   77                 0
   78         3: Slew step size:
   79                 Valid values for the step size LSBs:
   80                 1
   81                 2
   82                 4
   83                 16
   84                 32
   85                 64
   86                 128
   87                 256
   88 
   89 Example:
   90 dac@0 {
   91         #address-cells = <1>;
   92         #size-cells = <0>;
   93         compatible = "adi,ad5755";
   94         reg = <0>;
   95         spi-max-frequency = <1000000>;
   96         spi-cpha;
   97         adi,dc-dc-phase = <0>;
   98         adi,dc-dc-freq-hz = <410000>;
   99         adi,dc-dc-max-microvolt = <23000000>;
  100         channel@0 {
  101                 reg = <0>;
  102                 adi,mode = <4>;
  103                 adi,ext-current-sense-resistor;
  104                 adi,slew = <0 64000 1>;
  105         };
  106         channel@1 {
  107                 reg = <1>;
  108                 adi,mode = <4>;
  109                 adi,ext-current-sense-resistor;
  110                 adi,slew = <0 64000 1>;
  111         };
  112         channel@2 {
  113                 reg = <2>;
  114                 adi,mode = <4>;
  115                 adi,ext-current-sense-resistor;
  116                 adi,slew = <0 64000 1>;
  117         };
  118         channel@3 {
  119                 reg = <3>;
  120                 adi,mode = <4>;
  121                 adi,ext-current-sense-resistor;
  122                 adi,slew = <0 64000 1>;
  123         };
  124 };

Cache object: 3475b1a7b8ee321980f4eb37fa3d9f16


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.